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Message-Id: <20191113015932.12655-6-sashal@kernel.org>
Date: Tue, 12 Nov 2019 20:58:30 -0500
From: Sasha Levin <sashal@...nel.org>
To: linux-kernel@...r.kernel.org, stable@...r.kernel.org
Cc: Suzuki K Poulose <suzuki.poulose@....com>,
Christoffer Dall <cdall@...nel.org>,
Marc Zyngier <marc.zyngier@....com>,
Eric Auger <eric.auger@...hat.com>,
Sasha Levin <sashal@...nel.org>, kvmarm@...ts.cs.columbia.edu
Subject: [PATCH AUTOSEL 4.9 06/68] kvm: arm/arm64: Fix stage2_flush_memslot for 4 level page table
From: Suzuki K Poulose <suzuki.poulose@....com>
[ Upstream commit d2db7773ba864df6b4e19643dfc54838550d8049 ]
So far we have only supported 3 level page table with fixed IPA of
40bits, where PUD is folded. With 4 level page tables, we need
to check if the PUD entry is valid or not. Fix stage2_flush_memslot()
to do this check, before walking down the table.
Acked-by: Christoffer Dall <cdall@...nel.org>
Acked-by: Marc Zyngier <marc.zyngier@....com>
Reviewed-by: Eric Auger <eric.auger@...hat.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@....com>
Signed-off-by: Marc Zyngier <marc.zyngier@....com>
Signed-off-by: Sasha Levin <sashal@...nel.org>
---
arch/arm/kvm/mmu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index b3d268a79f057..bb0d5e21d60bd 100644
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -366,7 +366,8 @@ static void stage2_flush_memslot(struct kvm *kvm,
pgd = kvm->arch.pgd + stage2_pgd_index(addr);
do {
next = stage2_pgd_addr_end(addr, end);
- stage2_flush_puds(kvm, pgd, addr, next);
+ if (!stage2_pgd_none(*pgd))
+ stage2_flush_puds(kvm, pgd, addr, next);
} while (pgd++, addr = next, addr != end);
}
--
2.20.1
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