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Message-ID: <20191113110009.GC32742@smile.fi.intel.com>
Date: Wed, 13 Nov 2019 13:00:09 +0200
From: Andy Shevchenko <andriy.shevchenko@...el.com>
To: Dilip Kota <eswara.kota@...ux.intel.com>
Cc: gustavo.pimentel@...opsys.com, lorenzo.pieralisi@....com,
andrew.murray@....com, helgaas@...nel.org, jingoohan1@...il.com,
robh@...nel.org, martin.blumenstingl@...glemail.com,
linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, cheol.yong.kim@...el.com,
chuanhua.lei@...ux.intel.com, qi-ming.wu@...el.com
Subject: Re: [PATCH v6 2/3] dwc: PCI: intel: PCIe RC controller driver
On Wed, Nov 13, 2019 at 03:21:21PM +0800, Dilip Kota wrote:
> Add support to PCIe RC controller on Intel Gateway SoCs.
> PCIe controller is based of Synopsys DesignWare PCIe core.
>
> Intel PCIe driver requires Upconfigure support, Fast Training
> Sequence and link speed configurations. So adding the respective
> helper functions in the PCIe DesignWare framework.
> It also programs hardware autonomous speed during speed
> configuration so defining it in pci_regs.h.
> +#include <linux/of_irq.h>
> +#include <linux/of_platform.h>
I hardly see the use of above...
> + if (device_property_read_u32(dev, "reset-assert-ms", &lpp->rst_intrvl))
> + lpp->rst_intrvl = RESET_INTERVAL_MS;
...perhaps you need to add
#include <linux/property.h>
instead.
--
With Best Regards,
Andy Shevchenko
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