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Date:   Thu, 14 Nov 2019 11:52:47 +0800
From:   Dilip Kota <eswara.kota@...ux.intel.com>
To:     Andy Shevchenko <andriy.shevchenko@...el.com>
Cc:     gustavo.pimentel@...opsys.com, lorenzo.pieralisi@....com,
        andrew.murray@....com, helgaas@...nel.org, jingoohan1@...il.com,
        robh@...nel.org, martin.blumenstingl@...glemail.com,
        linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, cheol.yong.kim@...el.com,
        chuanhua.lei@...ux.intel.com, qi-ming.wu@...el.com
Subject: Re: [PATCH v6 2/3] dwc: PCI: intel: PCIe RC controller driver

On 11/13/2019 7:00 PM, Andy Shevchenko wrote:
> On Wed, Nov 13, 2019 at 03:21:21PM +0800, Dilip Kota wrote:
>> Add support to PCIe RC controller on Intel Gateway SoCs.
>> PCIe controller is based of Synopsys DesignWare PCIe core.
>>
>> Intel PCIe driver requires Upconfigure support, Fast Training
>> Sequence and link speed configurations. So adding the respective
>> helper functions in the PCIe DesignWare framework.
>> It also programs hardware autonomous speed during speed
>> configuration so defining it in pci_regs.h.
>> +#include <linux/of_irq.h>
>> +#include <linux/of_platform.h>
> I hardly see the use of above...
Thanks for pointing it. Yes, it can be removed. I have again cross 
checked all the header files , i see below files can also be removed.
#include <linux/interrupt.h>
#include <linux/of_irq.h>
#include <linux/of_pci.h>

>> +	if (device_property_read_u32(dev, "reset-assert-ms", &lpp->rst_intrvl))
>> +		lpp->rst_intrvl = RESET_INTERVAL_MS;
> ...perhaps you need to add
>
> #include <linux/property.h>
>
> instead.

I see this header file isĀ  already getting included in the driver 
through linux/phy/phy.h => linux/of.h (of.h has #include <linux/property.h>)

Thanks for reviewing the patch, i will update the driver and submit the 
next patch version.

Regards,
Dilip

>

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