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Message-ID: <1573702559-2744-3-git-send-email-peng.fan@nxp.com>
Date: Thu, 14 Nov 2019 03:38:17 +0000
From: Peng Fan <peng.fan@....com>
To: "sboyd@...nel.org" <sboyd@...nel.org>,
"shawnguo@...nel.org" <shawnguo@...nel.org>,
"s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
"festevam@...il.com" <festevam@...il.com>,
Abel Vesa <abel.vesa@....com>
CC: "kernel@...gutronix.de" <kernel@...gutronix.de>,
dl-linux-imx <linux-imx@....com>,
Aisheng Dong <aisheng.dong@....com>,
"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Leonard Crestez <leonard.crestez@....com>,
Alice Guo <alice.guo@....com>,
"will@...nel.org" <will@...nel.org>, Peng Fan <peng.fan@....com>
Subject: [PATCH V2 2/4] clk: imx: pll14xx: use readl to force write completed
From: Peng Fan <peng.fan@....com>
To ensure writes to clock registers have properly completed,
add a readl after writel_relaxed. Then we could make sure
when udelay, write has been completed.
Signed-off-by: Peng Fan <peng.fan@....com>
Cc: Will Deacon <will@...nel.org>
---
drivers/clk/imx/clk-pll14xx.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
index 5b7d41d43b3b..a8af949f0848 100644
--- a/drivers/clk/imx/clk-pll14xx.c
+++ b/drivers/clk/imx/clk-pll14xx.c
@@ -205,6 +205,12 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
(rate->sdiv << SDIV_SHIFT);
writel_relaxed(div_val, pll->base + 0x4);
+ /*
+ * readl will force write completed. There is a udelay below,
+ * we need make sure before udelay, write has been completed
+ */
+ readl(pll->base + 0x4);
+
/*
* According to SPEC, t3 - t2 need to be greater than
* 1us and 1/FREF, respectively.
--
2.16.4
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