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Message-ID: <CAL_Jsq+fdksCHQ1_NaizkM6dVWT1h2wocJpD4NB8K2dOO-yZ4Q@mail.gmail.com>
Date: Thu, 14 Nov 2019 19:34:47 -0600
From: Rob Herring <robh+dt@...nel.org>
To: Andreas Färber <afaerber@...e.de>
Cc: linux-realtek-soc@...ts.infradead.org,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Mark Rutland <mark.rutland@....com>, devicetree@...r.kernel.org
Subject: Re: [PATCH 5/7] ARM: dts: rtd1195: Introduce r-bus
On Sun, Nov 10, 2019 at 9:04 PM Andreas Färber <afaerber@...e.de> wrote:
>
> Model Realtek's register bus in DT.
>
> Signed-off-by: Andreas Färber <afaerber@...e.de>
> ---
> This could be squashed into the original RTD1195 patch.
>
> arch/arm/boot/dts/rtd1195.dtsi | 52 ++++++++++++++++++++++++------------------
> 1 file changed, 30 insertions(+), 22 deletions(-)
>
> diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/rtd1195.dtsi
> index a8cc2d23e7ef..3439647ecf97 100644
> --- a/arch/arm/boot/dts/rtd1195.dtsi
> +++ b/arch/arm/boot/dts/rtd1195.dtsi
> @@ -92,28 +92,36 @@
> <0x18100000 0x18100000 0x01000000>,
> <0x40000000 0x40000000 0xc0000000>;
>
> - wdt: watchdog@...07680 {
> - compatible = "realtek,rtd1295-watchdog";
> - reg = <0x18007680 0x100>;
> - clocks = <&osc27M>;
> - };
> -
> - uart0: serial@...07800 {
> - compatible = "snps,dw-apb-uart";
> - reg = <0x18007800 0x400>;
> - reg-shift = <2>;
> - reg-io-width = <4>;
> - clock-frequency = <27000000>;
> - status = "disabled";
> - };
> -
> - uart1: serial@...1b200 {
> - compatible = "snps,dw-apb-uart";
> - reg = <0x1801b200 0x100>;
> - reg-shift = <2>;
> - reg-io-width = <4>;
> - clock-frequency = <27000000>;
> - status = "disabled";
> + rbus: r-bus@...00000 {
Following node names should be generic: bus@...
> + compatible = "simple-bus";
> + reg = <0x18000000 0x100000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x18000000 0x100000>;
> +
> + wdt: watchdog@...0 {
> + compatible = "realtek,rtd1295-watchdog";
> + reg = <0x7680 0x100>;
> + clocks = <&osc27M>;
> + };
> +
> + uart0: serial@...0 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x7800 0x400>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clock-frequency = <27000000>;
> + status = "disabled";
> + };
> +
> + uart1: serial@...00 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x1b200 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clock-frequency = <27000000>;
> + status = "disabled";
> + };
> };
>
> gic: interrupt-controller@...11000 {
> --
> 2.16.4
>
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