| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20191116005240.15722-2-robh@kernel.org>
Date: Fri, 15 Nov 2019 18:52:39 -0600
From: Rob Herring <robh@...nel.org>
To: devicetree@...r.kernel.org
Cc: linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
Alan Douglas <adouglas@...ence.com>,
Scott Telford <stelford@...ence.com>,
Tom Joseph <tjoseph@...ence.com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Andrew Murray <andrew.murray@....com>
Subject: [PATCH 2/3] dt-bindings: PCI: Convert Cadence host to DT schema
Convert the Cadence PCIe host binding to DT schema.
The 'phy-names' definition is incomplete.
'vendor-id' and 'device-id' aren't listed as those are standard PCI
properties. They were incorrectly defined as 16-bit when they should be
32-bits (even though only 16-bits are used).
'cdns,max-outbound-regions' should really be removed. It serves no
purpose other than bounds checking 'ranges'. If 'ranges' is wrong for
the h/w, what's going to ensure 'cdns,max-outbound-regions' is correct.
'cdns,no-bar-match-nbits' is also suspect. This probably could be
determined from 'dma-ranges' using the sizes.
Cc: Alan Douglas <adouglas@...ence.com>
Cc: Scott Telford <stelford@...ence.com>
Cc: Tom Joseph <tjoseph@...ence.com>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@....com>
Cc: Andrew Murray <andrew.murray@....com>
Signed-off-by: Rob Herring <robh@...nel.org>
---
.../bindings/pci/cdns,cdns-pcie-host.txt | 66 -----------
.../bindings/pci/cdns,cdns-pcie-host.yaml | 106 ++++++++++++++++++
MAINTAINERS | 2 +-
3 files changed, 107 insertions(+), 67 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
deleted file mode 100644
index 91de69c713a9..000000000000
--- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
+++ /dev/null
@@ -1,66 +0,0 @@
-* Cadence PCIe host controller
-
-This PCIe controller inherits the base properties defined in
-host-generic-pci.txt.
-
-Required properties:
-- compatible: Should contain "cdns,cdns-pcie-host" to identify the IP used.
-- reg: Should contain the controller register base address, PCIe configuration
- window base address, and AXI interface region base address respectively.
-- reg-names: Must be "reg", "cfg" and "mem" respectively.
-- #address-cells: Set to <3>
-- #size-cells: Set to <2>
-- device_type: Set to "pci"
-- ranges: Ranges for the PCI memory and I/O regions
-- #interrupt-cells: Set to <1>
-- interrupt-map-mask and interrupt-map: Standard PCI properties to define the
- mapping of the PCIe interface to interrupt numbers.
-
-Optional properties:
-- cdns,max-outbound-regions: Set to maximum number of outbound regions
- (default 32)
-- cdns,no-bar-match-nbits: Set into the no BAR match register to configure the
- number of least significant bits kept during inbound (PCIe -> AXI) address
- translations (default 32)
-- vendor-id: The PCI vendor ID (16 bits, default is design dependent)
-- device-id: The PCI device ID (16 bits, default is design dependent)
-- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
- than one in the list. If only one PHY listed it must manage all lanes.
-- phy-names: List of names to identify the PHY.
-
-Example:
-
-pcie@...00000 {
- compatible = "cdns,cdns-pcie-host";
- device_type = "pci";
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x0 0xff>;
- linux,pci-domain = <0>;
- cdns,max-outbound-regions = <16>;
- cdns,no-bar-match-nbits = <32>;
- vendor-id = /bits/ 16 <0x17cd>;
- device-id = /bits/ 16 <0x0200>;
-
- reg = <0x0 0xfb000000 0x0 0x01000000>,
- <0x0 0x41000000 0x0 0x00001000>,
- <0x0 0x40000000 0x0 0x04000000>;
- reg-names = "reg", "cfg", "mem";
-
- ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
- <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
-
- #interrupt-cells = <0x1>;
-
- interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1
- 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1
- 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1
- 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>;
-
- interrupt-map-mask = <0x0 0x0 0x0 0x7>;
-
- msi-parent = <&its_pci>;
-
- phys = <&pcie_phy0>;
- phy-names = "pcie-phy";
-};
diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
new file mode 100644
index 000000000000..ada77e267b68
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence PCIe host controller
+
+maintainers:
+ - Alan Douglas <adouglas@...ence.com>
+ - Scott Telford <stelford@...ence.com>
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+ compatible:
+ const: cdns,cdns-pcie-host
+
+ reg:
+ maxItems: 3
+
+ reg-names:
+ items:
+ - const: reg
+ - const: cfg
+ - const: mem
+
+ cdns,max-outbound-regions:
+ description: maximum number of outbound regions
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 32
+ default: 32
+
+ cdns,no-bar-match-nbits:
+ description:
+ Set into the no BAR match register to configure the number of least
+ significant bits kept during inbound (PCIe -> AXI) address translations
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 32
+ default: 32
+
+ msi-parent: true
+
+ phys:
+ description:
+ One per lane if more than one in the list. If only one PHY listed it must
+ manage all lanes.
+ minItems: 1
+ maxItems: 16
+
+ phy-names:
+ items:
+ - const: pcie-phy
+ # FIXME: names when more than 1
+
+required:
+ - reg
+ - reg-names
+
+examples:
+ - |
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@...00000 {
+ compatible = "cdns,cdns-pcie-host";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ linux,pci-domain = <0>;
+ cdns,max-outbound-regions = <16>;
+ cdns,no-bar-match-nbits = <32>;
+ vendor-id = /bits/ 16 <0x17cd>;
+ device-id = /bits/ 16 <0x0200>;
+
+ reg = <0x0 0xfb000000 0x0 0x01000000>,
+ <0x0 0x41000000 0x0 0x00001000>,
+ <0x0 0x40000000 0x0 0x04000000>;
+ reg-names = "reg", "cfg", "mem";
+
+ ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
+ <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
+
+ #interrupt-cells = <0x1>;
+
+ interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1>,
+ <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1>,
+ <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1>,
+ <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>;
+
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+
+ msi-parent = <&its_pci>;
+
+ phys = <&pcie_phy0>;
+ phy-names = "pcie-phy";
+ };
+ };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 48a90f0833b8..21f3393c36e3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12416,7 +12416,7 @@ PCI DRIVER FOR CADENCE PCIE IP
M: Tom Joseph <tjoseph@...ence.com>
L: linux-pci@...r.kernel.org
S: Maintained
-F: Documentation/devicetree/bindings/pci/cdns,*.txt
+F: Documentation/devicetree/bindings/pci/cdns,*
F: drivers/pci/controller/pcie-cadence*
PCI DRIVER FOR FREESCALE LAYERSCAPE
--
2.20.1
Powered by blists - more mailing lists