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Date: Mon, 18 Nov 2019 14:45:39 -0800
From: Atish Patra <atish.patra@....com>
To: linux-kernel@...r.kernel.org
Cc: Atish Patra <atish.patra@....com>,
Albert Ou <aou@...s.berkeley.edu>,
Alexios Zavras <alexios.zavras@...el.com>,
Allison Randal <allison@...utok.net>,
Anup Patel <anup@...infault.org>, Gary Guo <gary@...yguo.net>,
linux-riscv@...ts.infradead.org, Mao Han <han_mao@...ky.com>,
Mike Rapoport <rppt@...ux.ibm.com>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Christoph Hellwig <hch@....de>,
Jonathan Behrens <behrensj@....edu>
Subject: [PATCH v3 4/4] RISC-V: Implement SBI v0.2 replacement extensions
Few v0.1 SBI calls are being replaced by new SBI calls that follows
v0.2 calling convention. The specification changes can be found at
https://github.com/riscv/riscv-sbi-doc/pull/27
Implement the replacement extensions that makes way for a better SBI
interface in future.
Signed-off-by: Atish Patra <atish.patra@....com>
---
arch/riscv/include/asm/sbi.h | 22 ++++++++++++++
arch/riscv/kernel/sbi.c | 57 ++++++++++++++++++++++++++++++++++++
2 files changed, 79 insertions(+)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 75ad7a190b1b..09beb0bfa3b4 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -19,6 +19,10 @@ enum sbi_ext_id {
SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
SBI_EXT_0_1_SHUTDOWN = 0x8,
SBI_EXT_BASE = 0x10,
+ SBI_EXT_TIME = 0x54494D45,
+ SBI_EXT_IPI = 0x735049,
+ SBI_EXT_RFENCE = 0x52464E43,
+
};
enum sbi_ext_base_fid {
@@ -31,6 +35,24 @@ enum sbi_ext_base_fid {
SBI_BASE_GET_MIMPID,
};
+enum sbi_ext_time_fid {
+ SBI_EXT_TIME_SET_TIMER = 0,
+};
+
+enum sbi_ext_ipi_fid {
+ SBI_EXT_IPI_SEND_IPI = 0,
+};
+
+enum sbi_ext_rfence_fid {
+ SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
+ SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
+ SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
+};
+
#define SBI_SPEC_VERSION_DEFAULT 0x1
#define SBI_SPEC_VERSION_MAJOR_OFFSET 24
#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index 6c864fd7fb95..02e7bf581183 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -120,6 +120,14 @@ void sbi_set_timer(uint64_t stime_value)
}
#endif
+#if __riscv_xlen == 32
+ sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value,
+ stime_value >> 32, 0, 0, 0, 0);
+#else
+ sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value, 0,
+ 0, 0, 0, 0);
+#endif
+
}
/**
@@ -130,6 +138,8 @@ void sbi_set_timer(uint64_t stime_value)
*/
void sbi_send_ipi(const unsigned long *hart_mask)
{
+ unsigned long hmask_val;
+ struct sbiret ret;
#ifdef CONFIG_RISCV_SBI_V01
if (sbi_spec_is_0_1()) {
sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask,
@@ -137,6 +147,16 @@ void sbi_send_ipi(const unsigned long *hart_mask)
return;
}
#endif
+ if (!hart_mask)
+ hmask_val = *(cpumask_bits(cpu_online_mask));
+ else
+ hmask_val = *hart_mask;
+
+ ret = sbi_ecall(SBI_EXT_IPI, SBI_EXT_IPI_SEND_IPI, *hart_mask,
+ 0, 0, 0, 0, 0);
+ if (ret.error)
+ pr_err("%s: failed with error [%d]\n", __func__,
+ sbi_err_map_linux_errno(ret.error));
}
/**
@@ -147,6 +167,8 @@ void sbi_send_ipi(const unsigned long *hart_mask)
*/
void sbi_remote_fence_i(const unsigned long *hart_mask)
{
+ unsigned long hmask_val;
+ struct sbiret ret;
#ifdef CONFIG_RISCV_SBI_V01
if (sbi_spec_is_0_1()) {
sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0,
@@ -154,6 +176,16 @@ void sbi_remote_fence_i(const unsigned long *hart_mask)
return;
}
#endif
+ if (!hart_mask)
+ hmask_val = *(cpumask_bits(cpu_online_mask));
+ else
+ hmask_val = *hart_mask;
+
+ ret = sbi_ecall(SBI_EXT_RFENCE, SBI_EXT_RFENCE_REMOTE_FENCE_I,
+ hmask_val, 0, 0, 0, 0, 0);
+ if (ret.error)
+ pr_err("%s: failed with error [%d]\n", __func__,
+ sbi_err_map_linux_errno(ret.error));
}
/**
@@ -169,6 +201,8 @@ void sbi_remote_sfence_vma(const unsigned long *hart_mask,
unsigned long start,
unsigned long size)
{
+ unsigned long hmask_val;
+ struct sbiret ret;
#ifdef CONFIG_RISCV_SBI_V01
if (sbi_spec_is_0_1()) {
sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
@@ -176,6 +210,17 @@ void sbi_remote_sfence_vma(const unsigned long *hart_mask,
return;
}
#endif
+ if (!hart_mask)
+ hmask_val = *(cpumask_bits(cpu_online_mask));
+ else
+ hmask_val = *hart_mask;
+
+ ret = sbi_ecall(SBI_EXT_RFENCE, SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
+ hmask_val, 0, start, size, 0, 0);
+
+ if (ret.error)
+ pr_err("%s: failed with error [%d]\n", __func__,
+ sbi_err_map_linux_errno(ret.error));
}
/**
@@ -194,6 +239,8 @@ void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
unsigned long size,
unsigned long asid)
{
+ struct sbiret ret;
+ unsigned long hmask_val;
#ifdef CONFIG_RISCV_SBI_V01
if (sbi_spec_is_0_1()) {
sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
@@ -201,6 +248,16 @@ void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
return;
}
#endif
+ if (!hart_mask)
+ hmask_val = *(cpumask_bits(cpu_online_mask));
+ else
+ hmask_val = *hart_mask;
+
+ ret = sbi_ecall(SBI_EXT_RFENCE, SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
+ hmask_val, 0, start, size, asid, 0);
+ if (ret.error)
+ pr_err("%s: failed with error [%d]\n", __func__,
+ sbi_err_map_linux_errno(ret.error));
}
/**
--
2.23.0
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