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Message-ID: <96bb7bcf-97b7-f6ca-3f4b-0610bb51a166@linux.intel.com>
Date: Mon, 18 Nov 2019 09:31:30 +0800
From: Lu Baolu <baolu.lu@...ux.intel.com>
To: Jacob Pan <jacob.jun.pan@...ux.intel.com>,
iommu@...ts.linux-foundation.org,
LKML <linux-kernel@...r.kernel.org>,
Joerg Roedel <joro@...tes.org>,
David Woodhouse <dwmw2@...radead.org>
Cc: baolu.lu@...ux.intel.com, "Tian, Kevin" <kevin.tian@...el.com>,
Raj Ashok <ashok.raj@...el.com>, Yi Liu <yi.l.liu@...el.com>,
Eric Auger <eric.auger@...hat.com>
Subject: Re: [PATCH 04/10] iommu/vt-d: Match CPU and IOMMU paging mode
Hi,
On 11/16/19 7:09 AM, Jacob Pan wrote:
> When setting up first level page tables for sharing with CPU, we need
> to ensure IOMMU can support no less than the levels supported by the
> CPU.
> It is not adequate, as in the current code, to set up 5-level paging
> in PASID entry First Level Paging Mode(FLPM) solely based on CPU.
>
> Fixes: 437f35e1cd4c8 ("iommu/vt-d: Add first level page table
> interface")
> Signed-off-by: Jacob Pan <jacob.jun.pan@...ux.intel.com>
Acked-by: Lu Baolu <baolu.lu@...ux.intel.com>
Best regards,
baolu
> ---
> drivers/iommu/intel-pasid.c | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/iommu/intel-pasid.c b/drivers/iommu/intel-pasid.c
> index 040a445be300..e7cb0b8a7332 100644
> --- a/drivers/iommu/intel-pasid.c
> +++ b/drivers/iommu/intel-pasid.c
> @@ -499,8 +499,16 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu,
> }
>
> #ifdef CONFIG_X86
> - if (cpu_feature_enabled(X86_FEATURE_LA57))
> - pasid_set_flpm(pte, 1);
> + /* Both CPU and IOMMU paging mode need to match */
> + if (cpu_feature_enabled(X86_FEATURE_LA57)) {
> + if (cap_5lp_support(iommu->cap)) {
> + pasid_set_flpm(pte, 1);
> + } else {
> + pr_err("VT-d has no 5-level paging support for CPU\n");
> + pasid_clear_entry(pte);
> + return -EINVAL;
> + }
> + }
> #endif /* CONFIG_X86 */
>
> pasid_set_domain_id(pte, did);
>
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