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Message-ID: <20191118101821.GD4345@gilmour.lan>
Date: Mon, 18 Nov 2019 11:18:21 +0100
From: Maxime Ripard <mripard@...nel.org>
To: Tian Yunhao <t123yh@...look.com>
Cc: Icenowy Zheng <icenowy@...c.io>, Chen-Yu Tsai <wens@...e.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH, v2] clk: sunxi-ng: v3s: Fix incorrect number of hw_clks.
Hi,
On Wed, Nov 13, 2019 at 09:23:59AM +0000, Tian Yunhao wrote:
> The hws field of sun8i_v3s_hw_clks has only 74
> members. However, the number specified by CLK_NUMBER
> is 77 (= CLK_I2S0 + 1). This leads to runtime segmentation
> fault that is not always reproducible.
>
> This patch corrects this behavior by separating clock
> numbers for V3 and V3S.
>
> Signed-off-by: Yunhao Tian <t123yh@...look.com>
Even though they are similar, the Signed-off-by doesn't match the
authorship.
> ---
> drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 4 ++--
> drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 3 ++-
> 2 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
> index 5c779eec454b..72a87dd0c0d8 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
> @@ -618,7 +618,7 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = {
> [CLK_MBUS] = &mbus_clk.common.hw,
> [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw,
> },
> - .num = CLK_NUMBER,
> + .num = CLK_NUMBER_V3S,
> };
>
> static struct clk_hw_onecell_data sun8i_v3_hw_clks = {
> @@ -700,7 +700,7 @@ static struct clk_hw_onecell_data sun8i_v3_hw_clks = {
> [CLK_MBUS] = &mbus_clk.common.hw,
> [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw,
> },
> - .num = CLK_NUMBER,
> + .num = CLK_NUMBER_V3,
There's not much point in having a defined CLK_NUMBER here, just use
the value you've defined it to (so CLK_I2S0 + 1 and CLK_PLL_DDR1 + 1)
Maxime
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