linux-kernel - Re: [Freedreno] [PATCH 2/4] drm/msm/gpu: add support for ocmem interconnect path

Open Source and information security mailing list archives

Message-ID: <0101016e7f3bc614-0b50ca10-6ca3-459e-831c-af9e18acbacf-000000@us-west-2.amazonses.com>
Date:   Mon, 18 Nov 2019 15:57:34 +0000
From:   Jordan Crouse <jcrouse@...eaurora.org>
To:     Brian Masney <masneyb@...tation.org>
Cc:     robdclark@...il.com, sean@...rly.run, robh+dt@...nel.org,
        mark.rutland@....com, devicetree@...r.kernel.org, airlied@...ux.ie,
        linux-arm-msm@...r.kernel.org, dianders@...omium.org,
        dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
        daniel@...ll.ch, freedreno@...ts.freedesktop.org
Subject: Re: [Freedreno] [PATCH 2/4] drm/msm/gpu: add support for ocmem
 interconnect path

On Sun, Nov 17, 2019 at 06:48:23AM -0500, Brian Masney wrote:
> Some A3xx and all A4xx Adreno GPUs do not have GMEM inside the GPU core
> and must use the On Chip MEMory (OCMEM) in order to be functional.
> There's a separate interconnect path that needs to be setup to OCMEM.
> Add support for this second path to the GPU core.
> 
> In the downstream MSM 3.4 sources, the two interconnect paths for the
> GPU are between:
> 
>   - MSM_BUS_MASTER_GRAPHICS_3D and MSM_BUS_SLAVE_EBI_CH0
>   - MSM_BUS_MASTER_V_OCMEM_GFX3D and MSM_BUS_SLAVE_OCMEM
> 
> Signed-off-by: Brian Masney <masneyb@...tation.org>
> ---
>  drivers/gpu/drm/msm/adreno/a6xx_gmu.c   |  6 +++---
>  drivers/gpu/drm/msm/adreno/adreno_gpu.c | 20 ++++++++++++++++----
>  drivers/gpu/drm/msm/msm_gpu.h           |  3 ++-
>  3 files changed, 21 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> index 85f14feafdec..7885e382fb8f 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> @@ -132,7 +132,7 @@ static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index)
>  	 * Eventually we will want to scale the path vote with the frequency but
>  	 * for now leave it at max so that the performance is nominal.
>  	 */
> -	icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216));
> +	icc_set_bw(gpu->gfx_mem_icc_path, 0, MBps_to_icc(7216));
>  }
>  
>  void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq)
> @@ -714,7 +714,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
>  	}
>  
>  	/* Set the bus quota to a reasonable value for boot */
> -	icc_set_bw(gpu->icc_path, 0, MBps_to_icc(3072));
> +	icc_set_bw(gpu->gfx_mem_icc_path, 0, MBps_to_icc(3072));
>  
>  	/* Enable the GMU interrupt */
>  	gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0);
> @@ -858,7 +858,7 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
>  		a6xx_gmu_shutdown(gmu);
>  
>  	/* Remove the bus vote */
> -	icc_set_bw(gpu->icc_path, 0, 0);
> +	icc_set_bw(gpu->gfx_mem_icc_path, 0, 0);
>  
>  	/*
>  	 * Make sure the GX domain is off before turning off the GMU (CX)
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> index 0783e4b5486a..d1cc021c012c 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> @@ -887,9 +887,20 @@ static int adreno_get_pwrlevels(struct device *dev,
>  	DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate);
>  
>  	/* Check for an interconnect path for the bus */
> -	gpu->icc_path = of_icc_get(dev, NULL);
> -	if (IS_ERR(gpu->icc_path))
> -		gpu->icc_path = NULL;
> +	gpu->gfx_mem_icc_path = of_icc_get(dev, "gfx-mem");
> +	if (!gpu->gfx_mem_icc_path) {
> +		/*
> +		 * Keep compatbility with device trees that don't have an
> +		 * interconnect-names property.
> +		 */
> +		gpu->gfx_mem_icc_path = of_icc_get(dev, NULL);
> +	}
> +	if (IS_ERR(gpu->gfx_mem_icc_path))
> +		gpu->gfx_mem_icc_path = NULL;
> +
> +	gpu->ocmem_icc_path = of_icc_get(dev, "ocmem");
> +	if (IS_ERR(gpu->ocmem_icc_path))
> +		gpu->ocmem_icc_path = NULL;

This is the part where I am reminded that icc_set_bw doesn't check
IS_ERR_OR_NULL and even worse, icc_put warns on IS_ERR and it makes 
me grumble.

>  	return 0;
>  }
> @@ -976,7 +987,8 @@ void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu)
>  	for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++)
>  		release_firmware(adreno_gpu->fw[i]);
>  
> -	icc_put(gpu->icc_path);
> +	icc_put(gpu->gfx_mem_icc_path);
> +	icc_put(gpu->ocmem_icc_path);
>  
>  	msm_gpu_cleanup(&adreno_gpu->base);
>  }
> diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
> index ab8f0f9c9dc8..e72e56f7b0ef 100644
> --- a/drivers/gpu/drm/msm/msm_gpu.h
> +++ b/drivers/gpu/drm/msm/msm_gpu.h
> @@ -111,7 +111,8 @@ struct msm_gpu {
>  	struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk;
>  	uint32_t fast_rate;
>  
> -	struct icc_path *icc_path;
> +	struct icc_path *gfx_mem_icc_path;
> +	struct icc_path *ocmem_icc_path;

I'm not sure if we want a bulk rename of the main path.  icc_path and
ocmem_icc_path seem to be reasonable names and not overly confusing especially
if we added some documentation to the header).

>  	/* Hang and Inactivity Detection:
>  	 */
> -- 
> 2.21.0
> 
> _______________________________________________
> Freedreno mailing list
> Freedreno@...ts.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/freedreno

-- 
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives