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Date:   Mon, 18 Nov 2019 18:06:24 +0000
From:   "Kammela, Gayatri" <gayatri.kammela@...el.com>
To:     "Mario.Limonciello@...l.com" <Mario.Limonciello@...l.com>,
        "platform-driver-x86@...r.kernel.org" 
        <platform-driver-x86@...r.kernel.org>
CC:     "Somayaji, Vishwanath" <vishwanath.somayaji@...el.com>,
        "dvhart@...radead.org" <dvhart@...radead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "Prestopine, Charles D" <charles.d.prestopine@...el.com>,
        "peterz@...radead.org" <peterz@...radead.org>,
        "Pandruvada, Srinivas" <srinivas.pandruvada@...el.com>,
        "andriy.shevchenko@...ux.intel.com" 
        <andriy.shevchenko@...ux.intel.com>,
        "Liang, Kan" <kan.liang@...el.com>,
        "Box, David E" <david.e.box@...el.com>,
        "Bhardwaj, Rajneesh" <rajneesh.bhardwaj@...el.com>,
        "Luck, Tony" <tony.luck@...el.com>
Subject: RE: [PATCH v3 7/7] platform/x86: Add Comet Lake (CML) platform
 support to intel_pmc_core driver

> >  /* Cannon Lake: PGD PFET Enable Ack Status Register(s) bitmap */
> > static const struct pmc_bit_map cnp_pfear_map[] = {
> > +	/* Reserved for Cannon Lake but valid for Comet Lake */
> >  	{"PMC",                 BIT(0)},
> >  	{"OPI-DMI",             BIT(1)},
> >  	{"SPI/eSPI",            BIT(2)},
> > @@ -879,6 +880,8 @@ static const struct x86_cpu_id intel_pmc_core_ids[]
> = {
> >  	INTEL_CPU_FAM6(TIGERLAKE_L, tgl_reg_map),
> >  	INTEL_CPU_FAM6(TIGERLAKE, tgl_reg_map),
> >  	INTEL_CPU_FAM6(ATOM_TREMONT, tgl_reg_map),
> > +	INTEL_CPU_FAM6(COMETLAKE, cnp_reg_map),
> > +	INTEL_CPU_FAM6(COMETLAKE_L, cnp_reg_map),
> >  	{}
> >  };
> >
> 
> Just a nit, that I'm not sure if there is a policy around.
> Shouldn't the order of these reflect the actual order they're available to the
> marketplace?  So CML may want to come earlier in the patch series to reflect
> that aspect.
 Hi Mario,  agreed! I will send this patch separately from the series as this is an urgent request from Dell.

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