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Message-ID: <0101016e80784451-873bf09d-3517-480d-80a2-c89750d0ae12-000000@us-west-2.amazonses.com>
Date: Mon, 18 Nov 2019 21:43:15 +0000
From: Sibi Sankar <sibis@...eaurora.org>
To: bjorn.andersson@...aro.org, jhugo@...eaurora.org,
robh+dt@...nel.org, jonathan@...ek.ca
Cc: ohad@...ery.com, mark.rutland@....com, p.zabel@...gutronix.de,
linux-arm-msm@...r.kernel.org, linux-remoteproc@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
agross@...nel.org, Sibi Sankar <sibis@...eaurora.org>
Subject: [PATCH 02/16] remoteproc: q6v5-mss: Streamline the MSS out of reset sequence
Streamline the MSS out of reset sequence to reuse common code across
MSM8998/MSM8996/MSM8974/MSM8916 SoCs.
Signed-off-by: Sibi Sankar <sibis@...eaurora.org>
---
drivers/remoteproc/qcom_q6v5_mss.c | 94 ++++++++++++++++--------------
1 file changed, 51 insertions(+), 43 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c
index 2becf6dade936..06a57db3238db 100644
--- a/drivers/remoteproc/qcom_q6v5_mss.c
+++ b/drivers/remoteproc/qcom_q6v5_mss.c
@@ -505,21 +505,21 @@ static int q6v5proc_reset(struct q6v5 *qproc)
}
goto pbl_wait;
- } else if (qproc->version == MSS_MSM8996 ||
- qproc->version == MSS_MSM8998) {
- int mem_pwr_ctl;
+ }
- /* Override the ACC value if required */
- if (qproc->version == MSS_MSM8996)
- writel(QDSP6SS_ACC_OVERRIDE_VAL,
- qproc->reg_base + QDSP6SS_STRAP_ACC);
+ /* Override the ACC value if required */
+ if (qproc->version == MSS_MSM8996)
+ writel(QDSP6SS_ACC_OVERRIDE_VAL,
+ qproc->reg_base + QDSP6SS_STRAP_ACC);
- /* Assert resets, stop core */
- val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
- val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
- writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
+ /* Assert resets, stop core */
+ val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
+ val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
+ writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
- /* BHS require xo cbcr to be enabled */
+ /* BHS require xo cbcr to be enabled */
+ if (qproc->version == MSS_MSM8996 ||
+ qproc->version == MSS_MSM8998) {
val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
val |= 0x1;
writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
@@ -533,26 +533,35 @@ static int q6v5proc_reset(struct q6v5 *qproc)
"xo cbcr enabling timed out (rc:%d)\n", ret);
return ret;
}
- /* Enable power block headswitch and wait for it to stabilize */
- val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+ }
+
+ /* Enable power block headswitch and wait for it to stabilize */
+ val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+ if (qproc->version == MSS_MSM8996 ||
+ qproc->version == MSS_MSM8998)
val |= QDSP6v56_BHS_ON;
- writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
- val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
- udelay(1);
-
- /* wait for BHS_EN_REST_ACK to be set */
- if (qproc->version == MSS_MSM8998) {
- ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_BHS_STATUS,
- val, (val & QDSP6SS_BHS_EN_REST_ACK),
- 1, BHS_CHECK_MAX_LOOPS);
- if (ret) {
- dev_err(qproc->dev,
- "QDSP6SS_BHS_EN_REST_ACK timedout\n");
- return -ETIMEDOUT;
- }
+ else
+ val |= QDSS_BHS_ON | QDSS_LDO_BYP;
+ writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+ val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+ udelay(1);
+
+ /* wait for BHS_EN_REST_ACK to be set */
+ if (qproc->version == MSS_MSM8998) {
+ ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_BHS_STATUS,
+ val, (val & QDSP6SS_BHS_EN_REST_ACK),
+ 1, BHS_CHECK_MAX_LOOPS);
+ if (ret) {
+ dev_err(qproc->dev,
+ "QDSP6SS_BHS_EN_REST_ACK timedout\n");
+ return -ETIMEDOUT;
}
+ }
+ if (qproc->version == MSS_MSM8996 ||
+ qproc->version == MSS_MSM8998) {
/* Put LDO in bypass mode */
+ val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
val |= QDSP6v56_LDO_BYP;
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
@@ -564,7 +573,11 @@ static int q6v5proc_reset(struct q6v5 *qproc)
/* Deassert memory peripheral sleep and L2 memory standby */
val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+ }
+ /* Turn on memories */
+ if (qproc->version == MSS_MSM8996 || qproc->version == MSS_MSM8998) {
+ int mem_pwr_ctl;
/* Turn on L1, L2, ETB and JU memories 1 at a time */
if (qproc->version == MSS_MSM8996) {
mem_pwr_ctl = QDSP6SS_MEM_PWR_CTL;
@@ -586,22 +599,7 @@ static int q6v5proc_reset(struct q6v5 *qproc)
val |= readl(qproc->reg_base + mem_pwr_ctl);
udelay(1);
}
- /* Remove word line clamp */
- val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
- val &= ~QDSP6v56_CLAMP_WL;
- writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
} else {
- /* Assert resets, stop core */
- val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
- val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
- writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
-
- /* Enable power block headswitch and wait for it to stabilize */
- val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
- val |= QDSS_BHS_ON | QDSS_LDO_BYP;
- writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
- val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
- udelay(1);
/*
* Turn on memories. L2 banks should be done individually
* to minimize inrush current.
@@ -617,7 +615,17 @@ static int q6v5proc_reset(struct q6v5 *qproc)
val |= Q6SS_L2DATA_SLP_NRET_N_0;
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
}
+
+ /* Remove word line clamp */
+ if (qproc->version == MSS_MSM8996 ||
+ qproc->version == MSS_MSM8998) {
+ val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+ val &= ~QDSP6v56_CLAMP_WL;
+ writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+ }
+
/* Remove IO clamp */
+ val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
val &= ~Q6SS_CLAMP_IO;
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
--
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