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Message-ID: <e98364c5-a859-7981-8ccf-f8e5b5069379@suse.de>
Date: Tue, 19 Nov 2019 21:56:48 +0100
From: Andreas Färber <afaerber@...e.de>
To: Marc Zyngier <maz@...nel.org>
Cc: linux-realtek-soc@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Aleix Roca Nonell <kernelrocks@...il.com>,
James Tai <james.tai@...ltek.com>,
Thomas Gleixner <tglx@...utronix.de>,
Jason Cooper <jason@...edaemon.net>
Subject: Re: [PATCH v4 2/8] irqchip: Add Realtek RTD1295 mux driver
Am 19.11.19 um 13:01 schrieb Marc Zyngier:
> On 2019-11-19 02:19, Andreas Färber wrote:
>> +static void rtd1195_mux_enable_irq(struct irq_data *data)
>> +{
>> + struct rtd1195_irq_mux_data *mux_data =
>> irq_data_get_irq_chip_data(data);
>> + unsigned long flags;
>> + u32 mask;
>> +
>> + mask = mux_data->info->isr_to_int_en_mask[data->hwirq];
>> + if (!mask)
>> + return;
>
> How can this happen? You've mapped the interrupt, so it exists.
> I can't see how you can decide to fail such enable.
The [UMSK_]ISR bits and the SCPU_INT_EN bits are not (all) the same.
My ..._isr_to_scpu_int_en[] arrays have 32 entries for O(1) lookup, but
are sparsely populated. So there are circumstances such as WDOG_NMI as
well as reserved bits that we cannot enable. This check should be
identical to v3; the equivalent mask check inside the interrupt handler
was extended with "mask &&" to do the same in this v4.
The other question I'll need to dig into, it's been two years since I
wrote that code - first very simple guesswork, then more elaborate
quirks like the above.
Regards,
Andreas
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