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Date: Tue, 19 Nov 2019 16:22:54 -0800 From: Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com> To: andriy.shevchenko@...el.com Cc: platform-driver-x86@...r.kernel.org, linux-kernel@...r.kernel.org, prarit@...hat.com, Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com> Subject: [PATCH] tools/power/x86/intel-speed-select: Display TRL buckets for just base config level When only base config level is present, this tool is displaying TRL (Turbo-ratio-limits) by reading legacy MSR. In this case, also present core count for TRL by reading MSR 0x1AE. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com> --- tools/power/x86/intel-speed-select/isst-core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/power/x86/intel-speed-select/isst-core.c b/tools/power/x86/intel-speed-select/isst-core.c index aa19c9998e6c..d14c7bcd327a 100644 --- a/tools/power/x86/intel-speed-select/isst-core.c +++ b/tools/power/x86/intel-speed-select/isst-core.c @@ -681,6 +681,7 @@ int isst_get_process_ctdp(int cpu, int tdp_level, struct isst_pkg_ctdp *pkg_dev) } isst_get_get_trl_from_msr(cpu, ctdp_level->trl_sse_active_cores); + isst_get_trl_bucket_info(cpu, &ctdp_level->buckets_info); continue; } -- 2.17.2
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