| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20191120051509.GS18024@yoga>
Date: Tue, 19 Nov 2019 21:15:09 -0800
From: Bjorn Andersson <bjorn.andersson@...aro.org>
To: Niklas Cassel <niklas.cassel@...aro.org>
Cc: Andy Gross <agross@...nel.org>, linux-arm-msm@...r.kernel.org,
amit.kucheria@...aro.org, sboyd@...nel.org, vireshk@...nel.org,
ulf.hansson@...aro.org, Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v6 3/5] arm64: dts: qcom: qcs404: Add CPR and populate
OPP table
On Tue 19 Nov 07:46 PST 2019, Niklas Cassel wrote:
> Add CPR and populate OPP table.
>
Reviewed-by: Bjorn Andersson <bjorn.andersson@...aro.org>
> Co-developed-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@...aro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@...aro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@...aro.org>
> ---
> arch/arm64/boot/dts/qcom/qcs404.dtsi | 132 +++++++++++++++++++++++++--
> 1 file changed, 124 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> index d03782e7bc11..30b9c7f8f200 100644
> --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> @@ -44,7 +44,8 @@
> #cooling-cells = <2>;
> clocks = <&apcs_glb>;
> operating-points-v2 = <&cpu_opp_table>;
> - cpu-supply = <&pms405_s3>;
> + power-domains = <&cpr>;
> + power-domain-names = "cpr";
> };
>
> CPU1: cpu@101 {
> @@ -57,7 +58,8 @@
> #cooling-cells = <2>;
> clocks = <&apcs_glb>;
> operating-points-v2 = <&cpu_opp_table>;
> - cpu-supply = <&pms405_s3>;
> + power-domains = <&cpr>;
> + power-domain-names = "cpr";
> };
>
> CPU2: cpu@102 {
> @@ -70,7 +72,8 @@
> #cooling-cells = <2>;
> clocks = <&apcs_glb>;
> operating-points-v2 = <&cpu_opp_table>;
> - cpu-supply = <&pms405_s3>;
> + power-domains = <&cpr>;
> + power-domain-names = "cpr";
> };
>
> CPU3: cpu@103 {
> @@ -83,7 +86,8 @@
> #cooling-cells = <2>;
> clocks = <&apcs_glb>;
> operating-points-v2 = <&cpu_opp_table>;
> - cpu-supply = <&pms405_s3>;
> + power-domains = <&cpr>;
> + power-domain-names = "cpr";
> };
>
> L2_0: l2-cache {
> @@ -107,20 +111,37 @@
> };
>
> cpu_opp_table: cpu-opp-table {
> - compatible = "operating-points-v2";
> + compatible = "operating-points-v2-kryo-cpu";
> opp-shared;
>
> opp-1094400000 {
> opp-hz = /bits/ 64 <1094400000>;
> - opp-microvolt = <1224000 1224000 1224000>;
> + required-opps = <&cpr_opp1>;
> };
> opp-1248000000 {
> opp-hz = /bits/ 64 <1248000000>;
> - opp-microvolt = <1288000 1288000 1288000>;
> + required-opps = <&cpr_opp2>;
> };
> opp-1401600000 {
> opp-hz = /bits/ 64 <1401600000>;
> - opp-microvolt = <1384000 1384000 1384000>;
> + required-opps = <&cpr_opp3>;
> + };
> + };
> +
> + cpr_opp_table: cpr-opp-table {
> + compatible = "operating-points-v2-qcom-level";
> +
> + cpr_opp1: opp1 {
> + opp-level = <1>;
> + qcom,opp-fuse-level = <1>;
> + };
> + cpr_opp2: opp2 {
> + opp-level = <2>;
> + qcom,opp-fuse-level = <2>;
> + };
> + cpr_opp3: opp3 {
> + opp-level = <3>;
> + qcom,opp-fuse-level = <3>;
> };
> };
>
> @@ -310,6 +331,62 @@
> tsens_caldata: caldata@d0 {
> reg = <0x1f8 0x14>;
> };
> + cpr_efuse_speedbin: speedbin@13c {
> + reg = <0x13c 0x4>;
> + bits = <2 3>;
> + };
> + cpr_efuse_quot_offset1: qoffset1@231 {
> + reg = <0x231 0x4>;
> + bits = <4 7>;
> + };
> + cpr_efuse_quot_offset2: qoffset2@232 {
> + reg = <0x232 0x4>;
> + bits = <3 7>;
> + };
> + cpr_efuse_quot_offset3: qoffset3@233 {
> + reg = <0x233 0x4>;
> + bits = <2 7>;
> + };
> + cpr_efuse_init_voltage1: ivoltage1@229 {
> + reg = <0x229 0x4>;
> + bits = <4 6>;
> + };
> + cpr_efuse_init_voltage2: ivoltage2@22a {
> + reg = <0x22a 0x4>;
> + bits = <2 6>;
> + };
> + cpr_efuse_init_voltage3: ivoltage3@22b {
> + reg = <0x22b 0x4>;
> + bits = <0 6>;
> + };
> + cpr_efuse_quot1: quot1@22b {
> + reg = <0x22b 0x4>;
> + bits = <6 12>;
> + };
> + cpr_efuse_quot2: quot2@22d {
> + reg = <0x22d 0x4>;
> + bits = <2 12>;
> + };
> + cpr_efuse_quot3: quot3@230 {
> + reg = <0x230 0x4>;
> + bits = <0 12>;
> + };
> + cpr_efuse_ring1: ring1@228 {
> + reg = <0x228 0x4>;
> + bits = <0 3>;
> + };
> + cpr_efuse_ring2: ring2@228 {
> + reg = <0x228 0x4>;
> + bits = <4 3>;
> + };
> + cpr_efuse_ring3: ring3@229 {
> + reg = <0x229 0x4>;
> + bits = <0 3>;
> + };
> + cpr_efuse_revision: revision@218 {
> + reg = <0x218 0x4>;
> + bits = <3 3>;
> + };
> };
>
> rng: rng@...00 {
> @@ -952,6 +1029,45 @@
> clocks = <&sleep_clk>;
> };
>
> + cpr: power-controller@...8000 {
> + compatible = "qcom,qcs404-cpr", "qcom,cpr";
> + reg = <0x0b018000 0x1000>;
> + interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&xo_board>;
> + clock-names = "ref";
> + vdd-apc-supply = <&pms405_s3>;
> + #power-domain-cells = <0>;
> + operating-points-v2 = <&cpr_opp_table>;
> + acc-syscon = <&tcsr>;
> +
> + nvmem-cells = <&cpr_efuse_quot_offset1>,
> + <&cpr_efuse_quot_offset2>,
> + <&cpr_efuse_quot_offset3>,
> + <&cpr_efuse_init_voltage1>,
> + <&cpr_efuse_init_voltage2>,
> + <&cpr_efuse_init_voltage3>,
> + <&cpr_efuse_quot1>,
> + <&cpr_efuse_quot2>,
> + <&cpr_efuse_quot3>,
> + <&cpr_efuse_ring1>,
> + <&cpr_efuse_ring2>,
> + <&cpr_efuse_ring3>,
> + <&cpr_efuse_revision>;
> + nvmem-cell-names = "cpr_quotient_offset1",
> + "cpr_quotient_offset2",
> + "cpr_quotient_offset3",
> + "cpr_init_voltage1",
> + "cpr_init_voltage2",
> + "cpr_init_voltage3",
> + "cpr_quotient1",
> + "cpr_quotient2",
> + "cpr_quotient3",
> + "cpr_ring_osc1",
> + "cpr_ring_osc2",
> + "cpr_ring_osc3",
> + "cpr_fuse_revision";
> + };
> +
> timer@...0000 {
> #address-cells = <1>;
> #size-cells = <1>;
> --
> 2.23.0
>
Powered by blists - more mailing lists