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Message-ID: <157425606029.12247.1129726844288422234.tip-bot2@tip-bot2>
Date: Wed, 20 Nov 2019 13:21:00 -0000
From: "tip-bot2 for Maulik Shah" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: Maulik Shah <mkshah@...eaurora.org>,
Lina Iyer <ilina@...eaurora.org>,
Marc Zyngier <maz@...nel.org>,
Stephen Boyd <swboyd@...omium.org>,
Ingo Molnar <mingo@...nel.org>, Borislav Petkov <bp@...en8.de>,
linux-kernel@...r.kernel.org
Subject: [tip: irq/core] irqchip/qcom-pdc: Add irqchip set/get state calls
The following commit has been merged into the irq/core branch of tip:
Commit-ID: e71374c07564536d38caed3e80a1ff1c4609161d
Gitweb: https://git.kernel.org/tip/e71374c07564536d38caed3e80a1ff1c4609161d
Author: Maulik Shah <mkshah@...eaurora.org>
AuthorDate: Fri, 15 Nov 2019 15:11:50 -07:00
Committer: Marc Zyngier <maz@...nel.org>
CommitterDate: Sat, 16 Nov 2019 10:22:01
irqchip/qcom-pdc: Add irqchip set/get state calls
Add irqchip calls to set/get interrupt state from the parent interrupt
controller. When GPIOs are renabled as interrupt lines, it is desirable
to clear the interrupt state at the GIC. This avoids any unwanted
interrupt as a result of stale pending state recorded when the line was
used as a GPIO.
Signed-off-by: Maulik Shah <mkshah@...eaurora.org>
[Lina: updated commit text, rearranged code]
Signed-off-by: Lina Iyer <ilina@...eaurora.org>
Signed-off-by: Marc Zyngier <maz@...nel.org>
Reviewed-by: Stephen Boyd <swboyd@...omium.org>
Link: https://lore.kernel.org/r/1573855915-9841-8-git-send-email-ilina@codeaurora.org
---
drivers/irqchip/qcom-pdc.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
index 4f2c762..6ae9e1f 100644
--- a/drivers/irqchip/qcom-pdc.c
+++ b/drivers/irqchip/qcom-pdc.c
@@ -5,6 +5,7 @@
#include <linux/err.h>
#include <linux/init.h>
+#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
@@ -50,6 +51,26 @@ static u32 pdc_reg_read(int reg, u32 i)
return readl_relaxed(pdc_base + reg + i * sizeof(u32));
}
+static int qcom_pdc_gic_get_irqchip_state(struct irq_data *d,
+ enum irqchip_irq_state which,
+ bool *state)
+{
+ if (d->hwirq == GPIO_NO_WAKE_IRQ)
+ return 0;
+
+ return irq_chip_get_parent_state(d, which, state);
+}
+
+static int qcom_pdc_gic_set_irqchip_state(struct irq_data *d,
+ enum irqchip_irq_state which,
+ bool value)
+{
+ if (d->hwirq == GPIO_NO_WAKE_IRQ)
+ return 0;
+
+ return irq_chip_set_parent_state(d, which, value);
+}
+
static void pdc_enable_intr(struct irq_data *d, bool on)
{
int pin_out = d->hwirq;
@@ -178,6 +199,8 @@ static struct irq_chip qcom_pdc_gic_chip = {
.irq_unmask = qcom_pdc_gic_unmask,
.irq_disable = qcom_pdc_gic_disable,
.irq_enable = qcom_pdc_gic_enable,
+ .irq_get_irqchip_state = qcom_pdc_gic_get_irqchip_state,
+ .irq_set_irqchip_state = qcom_pdc_gic_set_irqchip_state,
.irq_retrigger = irq_chip_retrigger_hierarchy,
.irq_set_type = qcom_pdc_gic_set_type,
.flags = IRQCHIP_MASK_ON_SUSPEND |
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