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Message-ID: <157425606074.12247.1499986640247864555.tip-bot2@tip-bot2>
Date: Wed, 20 Nov 2019 13:21:00 -0000
From: "tip-bot2 for Lina Iyer" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: Lina Iyer <ilina@...eaurora.org>, Marc Zyngier <maz@...nel.org>,
Stephen Boyd <swboyd@...omium.org>,
Ingo Molnar <mingo@...nel.org>, Borislav Petkov <bp@...en8.de>,
linux-kernel@...r.kernel.org
Subject: [tip: irq/core] irqchip/qcom-pdc: Do not toggle IRQ_ENABLE during mask/unmask
The following commit has been merged into the irq/core branch of tip:
Commit-ID: da3f875a4189e643f8eec7f0bffa39c90d3418c6
Gitweb: https://git.kernel.org/tip/da3f875a4189e643f8eec7f0bffa39c90d3418c6
Author: Lina Iyer <ilina@...eaurora.org>
AuthorDate: Fri, 15 Nov 2019 15:11:46 -07:00
Committer: Marc Zyngier <maz@...nel.org>
CommitterDate: Sat, 16 Nov 2019 10:20:49
irqchip/qcom-pdc: Do not toggle IRQ_ENABLE during mask/unmask
When an interrupt is to be serviced, the convention is to mask the
interrupt at the chip and unmask after servicing the interrupt. Enabling
and disabling the interrupt at the PDC irqchip causes an interrupt storm
due to the way dual edge interrupts are handled in hardware.
Skip configuring the PDC when the IRQ is masked and unmasked, instead
use the irq_enable/irq_disable callbacks to toggle the IRQ_ENABLE
register at the PDC. The PDC's IRQ_ENABLE register is only used during
the monitoring mode when the system is asleep and is not needed for
active mode detection.
Signed-off-by: Lina Iyer <ilina@...eaurora.org>
Signed-off-by: Marc Zyngier <maz@...nel.org>
Reviewed-by: Stephen Boyd <swboyd@...omium.org>
Link: https://lore.kernel.org/r/1573855915-9841-4-git-send-email-ilina@codeaurora.org
---
drivers/irqchip/qcom-pdc.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
index 690cf10..527c29e 100644
--- a/drivers/irqchip/qcom-pdc.c
+++ b/drivers/irqchip/qcom-pdc.c
@@ -63,15 +63,25 @@ static void pdc_enable_intr(struct irq_data *d, bool on)
raw_spin_unlock(&pdc_lock);
}
-static void qcom_pdc_gic_mask(struct irq_data *d)
+static void qcom_pdc_gic_disable(struct irq_data *d)
{
pdc_enable_intr(d, false);
+ irq_chip_disable_parent(d);
+}
+
+static void qcom_pdc_gic_enable(struct irq_data *d)
+{
+ pdc_enable_intr(d, true);
+ irq_chip_enable_parent(d);
+}
+
+static void qcom_pdc_gic_mask(struct irq_data *d)
+{
irq_chip_mask_parent(d);
}
static void qcom_pdc_gic_unmask(struct irq_data *d)
{
- pdc_enable_intr(d, true);
irq_chip_unmask_parent(d);
}
@@ -148,6 +158,8 @@ static struct irq_chip qcom_pdc_gic_chip = {
.irq_eoi = irq_chip_eoi_parent,
.irq_mask = qcom_pdc_gic_mask,
.irq_unmask = qcom_pdc_gic_unmask,
+ .irq_disable = qcom_pdc_gic_disable,
+ .irq_enable = qcom_pdc_gic_enable,
.irq_retrigger = irq_chip_retrigger_hierarchy,
.irq_set_type = qcom_pdc_gic_set_type,
.flags = IRQCHIP_MASK_ON_SUSPEND |
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