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Message-ID: <20191121072829.vitly7altcvlt4sj@pengutronix.de>
Date: Thu, 21 Nov 2019 08:28:29 +0100
From: Uwe Kleine-König
<u.kleine-koenig@...gutronix.de>
To: Clément Péron <peron.clem@...il.com>
Cc: Thierry Reding <thierry.reding@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Maxime Ripard <mripard@...nel.org>,
Chen-Yu Tsai <wens@...e.org>,
Philipp Zabel <pza@...gutronix.de>, linux-pwm@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-sunxi@...glegroups.com,
Jernej Skrabec <jernej.skrabec@...l.net>
Subject: Re: [PATCH v7 4/8] pwm: sun4i: Add an optional probe for bus clock
Hello Clément,
On Tue, Nov 19, 2019 at 06:53:15PM +0100, Clément Péron wrote:
> + /*
> + * We're keeping the bus clock on for the sake of simplicity.
> + * Actually it only needs to be on for hardware register accesses.
> + */
> + ret = clk_prepare_enable(pwm->bus_clk);
> + if (ret) {
> + dev_err(&pdev->dev, "Cannot prepare and enable bus_clk\n");
Maybe add the error code to the message?
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | https://www.pengutronix.de/ |
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