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Message-Id: <20191121140220.38030-2-helgaas@kernel.org>
Date: Thu, 21 Nov 2019 08:02:14 -0600
From: Bjorn Helgaas <helgaas@...nel.org>
To: linux-pci@...r.kernel.org
Cc: Alex Deucher <alexdeucher@...il.com>,
Frederick Lawler <fred@...dlawl.com>,
Christian Koenig <christian.koenig@....com>,
Chunming Zhou <David1.Zhou@....com>,
Dave Airlie <airlied@...ux.ie>,
Daniel Vetter <daniel@...ll.ch>, linux-kernel@...r.kernel.org,
dri-devel@...ts.freedesktop.org, amd-gfx@...ts.freedesktop.org,
Bjorn Helgaas <bhelgaas@...gle.com>,
Alex Deucher <alexander.deucher@....com>
Subject: [PATCH 1/7] PCI: Add #defines for Enter Compliance, Transmit Margin
From: Bjorn Helgaas <bhelgaas@...gle.com>
Add definitions for the Enter Compliance and Transmit Margin fields of the
PCIe Link Control 2 register.
Link: https://lore.kernel.org/r/20191112173503.176611-2-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@...gle.com>
Reviewed-by: Alex Deucher <alexander.deucher@....com>
---
include/uapi/linux/pci_regs.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 29d6e93fd15e..5869e5778a05 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -673,6 +673,8 @@
#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
#define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
+#define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */
+#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */
#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */
--
2.24.0.432.g9d3f5f5b63-goog
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