linux-kernel - Re: [PATCH][next] scsi: pm80xx: fix logic to break out of loop when register value is 2 or 3

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Message-ID: <CAMGffE=dHSO8jW4+iVe7xe5n6esdEb0D9V61XvFr3=a-MAMJJw@mail.gmail.com>
Date:   Fri, 22 Nov 2019 09:53:43 +0100
From:   Jinpu Wang <jinpu.wang@...ud.ionos.com>
To:     Colin King <colin.king@...onical.com>
Cc:     "James E . J . Bottomley" <jejb@...ux.ibm.com>,
        "Martin K . Petersen" <martin.petersen@...cle.com>,
        Deepak Ukey <Deepak.Ukey@...rochip.com>,
        Viswas G <Viswas.G@...rochip.com>,
        Linux SCSI Mailinglist <linux-scsi@...r.kernel.org>,
        kernel-janitors@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH][next] scsi: pm80xx: fix logic to break out of loop when
 register value is 2 or 3

On Wed, Nov 20, 2019 at 2:50 PM Colin King <colin.king@...onical.com> wrote:
>
> From: Colin Ian King <colin.king@...onical.com>
>
> The condition (reg_val != 2) || (reg_val != 3) will always be true because
> reg_val cannot be equal to two different values at the same time. Fix this
> by replacing the || operator with && so that the loop will loop if reg_val
> is not a 2 and not a 3 as was originally intended.
>
> Addresses-Coverity: ("Constant expression result")
> Fixes: 50dc2f221455 ("scsi: pm80xx: Modified the logic to collect fatal dump")
> Signed-off-by: Colin Ian King <colin.king@...onical.com>
looks fine. thanks Colin.
Acked-by: Jack Wang <jinpu.wang@...ud.ionos.com>
> ---
>  drivers/scsi/pm8001/pm80xx_hwi.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/scsi/pm8001/pm80xx_hwi.c b/drivers/scsi/pm8001/pm80xx_hwi.c
> index 19601138e889..d41908b23760 100644
> --- a/drivers/scsi/pm8001/pm80xx_hwi.c
> +++ b/drivers/scsi/pm8001/pm80xx_hwi.c
> @@ -348,7 +348,7 @@ ssize_t pm80xx_get_fatal_dump(struct device *cdev,
>                         do {
>                                 reg_val = pm8001_mr32(fatal_table_address,
>                                         MPI_FATAL_EDUMP_TABLE_STATUS);
> -                       } while (((reg_val != 2) || (reg_val != 3)) &&
> +                       } while (((reg_val != 2) && (reg_val != 3)) &&
>                                         time_before(jiffies, start));
>
>                         if (reg_val < 2) {
> --
> 2.24.0
>