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Message-ID: <20191125170345.GB30891@e121166-lin.cambridge.arm.com>
Date: Mon, 25 Nov 2019 17:03:45 +0000
From: Lorenzo Pieralisi <lorenzo.pieralisi@....com>
To: Dilip Kota <eswara.kota@...ux.intel.com>
Cc: gustavo.pimentel@...opsys.com, andrew.murray@....com,
helgaas@...nel.org, jingoohan1@...il.com, robh@...nel.org,
martin.blumenstingl@...glemail.com, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, andriy.shevchenko@...el.com,
linux-kernel@...r.kernel.org, cheol.yong.kim@...el.com,
chuanhua.lei@...ux.intel.com, qi-ming.wu@...el.com
Subject: Re: [PATCH v9 0/3] PCI: Add Intel PCIe Driver and respective
dt-binding yaml file
On Thu, Nov 21, 2019 at 05:31:17PM +0800, Dilip Kota wrote:
> Intel PCIe is Synopsys based controller. Intel PCIe driver uses
> DesignWare PCIe framework for host initialization and register
> configurations.
>
> Dilip Kota (3):
> dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller
> dwc: PCI: intel: PCIe RC controller driver
"PCI: dwc: ..."
You should follow other commit logs in history as a general
rule to make them uniform, I reordered it.
> PCI: artpec6: Configure FTS with dwc helper function
>
> .../devicetree/bindings/pci/intel-gw-pcie.yaml | 138 ++++++
> drivers/pci/controller/dwc/Kconfig | 10 +
> drivers/pci/controller/dwc/Makefile | 1 +
> drivers/pci/controller/dwc/pcie-artpec6.c | 8 +-
> drivers/pci/controller/dwc/pcie-designware.c | 57 +++
> drivers/pci/controller/dwc/pcie-designware.h | 12 +
> drivers/pci/controller/dwc/pcie-intel-gw.c | 545 +++++++++++++++++++++
> include/uapi/linux/pci_regs.h | 1 +
> 8 files changed, 765 insertions(+), 7 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
> create mode 100644 drivers/pci/controller/dwc/pcie-intel-gw.c
Applied to pci/dwc, we should be able to merge it for v5.5.
Lorenzo
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