linux-kernel - Re: [linux-sunxi] [PATCH] media: sun6i-csi: Fix incorrect HSYNC/VSYNC/PCLK polarity configuration

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Date:   Thu, 28 Nov 2019 04:06:53 +0100
From:   Ondřej Jirman <megous@...ous.com>
To:     Yong <yong.deng@...ewell.com>
Cc:     linux-sunxi@...glegroups.com,
        Mauro Carvalho Chehab <mchehab@...nel.org>,
        Maxime Ripard <mripard@...nel.org>,
        Chen-Yu Tsai <wens@...e.org>,
        "open list:CSI DRIVERS FOR ALLWINNER V3s" 
        <linux-media@...r.kernel.org>,
        "moderated list:ARM/Allwinner sunXi SoC support" 
        <linux-arm-kernel@...ts.infradead.org>,
        open list <linux-kernel@...r.kernel.org>
Subject: Re: [linux-sunxi] [PATCH] media: sun6i-csi: Fix incorrect
 HSYNC/VSYNC/PCLK polarity configuration

Hi,

On Thu, Nov 28, 2019 at 10:26:08AM +0800, Yong wrote:
> Hi Ondrej,
> 
> This has been discussed.
> And Maxime sent a patch for this: 
> https://www.mail-archive.com/linux-media@vger.kernel.org/msg127149.html

Thanks for pointing to the previous patch. But that patch doesn't make any
sense, and breaks things for me, and doesn't even match BSP code, which 
has no such reversal, and works fine with about 30 cam drivers.

Also how do you explain my findings?

My camera is sending correct signals, verified by looking at them actually (see
below), and CSI is not receiving the image. I have to flip HSYNC/VSYNC to be
oposite of that what CSI driver expects and I get a noisy image and if I fix
PCLK polarity too, the noise goes away, which means now I'm also sampling when
the data are stable and not when they're changing.

Here: (output from my cam, that I configured to have VSYNC ACTIVE LOW, HSYNC
ACTIVE LOW) And the signal is clearly that, as you can see yourself:

  https://megous.com/dl/tmp/98df81b7ed0126ec.png

The above signals are received with CSI driver configured with
V4L2_MBUS_VSYNC_ACTIVE_HIGH V4L2_MBUS_HSYNC_ACTIVE_HIGH. So CSI driver is
clearly wrong.

I think this is pretty clear the driver is buggy. At least for A83T SoC.

I'm not sure what Maxime found out, but he should probably re-check his
findings. Maxime, can you comment on this?

regards,
	o.

> On Thu, 28 Nov 2019 03:02:59 +0100
> Ondrej Jirman <megous@...ous.com> wrote:
> 
> > This was discovered by writing a new camera driver and wondering, why
> > hsync/vsync polarity setting behaves in reverse to what would be
> > expected. Verified by looking at the actual signals and the SoC
> > user manual.
> > 
> > Fixes: 5cc7522d8965 ("media: sun6i: Add support for Allwinner CSI V3s")
> > Signed-off-by: Ondrej Jirman <megous@...ous.com>
> > ---
> >  drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
> > index f17e5550602d..98bbcca59a90 100644
> > --- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
> > +++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
> > @@ -417,12 +417,12 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
> >  		if (flags & V4L2_MBUS_FIELD_EVEN_LOW)
> >  			cfg |= CSI_IF_CFG_FIELD_POSITIVE;
> >  
> > -		if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
> > +		if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
> >  			cfg |= CSI_IF_CFG_VREF_POL_POSITIVE;
> > -		if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
> > +		if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
> >  			cfg |= CSI_IF_CFG_HREF_POL_POSITIVE;
> >  
> > -		if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
> > +		if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
> >  			cfg |= CSI_IF_CFG_CLK_POL_FALLING_EDGE;
> >  		break;
> >  	case V4L2_MBUS_BT656:
> > -- 
> > 2.24.0
> > 
> > -- 
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> > To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20191128020259.1338188-1-megous%40megous.com.
> 
> 
> Thanks,
> Yong