linux-kernel - Re: [PATCH v3 5/7] PCI: brcmstb: add MSI capability

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20191129154629.GF43905@e119886-lin.cambridge.arm.com>
Date:   Fri, 29 Nov 2019 15:46:30 +0000
From:   Andrew Murray <andrew.murray@....com>
To:     Nicolas Saenz Julienne <nsaenzjulienne@...e.de>
Cc:     maz@...nel.org, linux-kernel@...r.kernel.org,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Eric Anholt <eric@...olt.net>,
        Stefan Wahren <wahrenst@....net>,
        Florian Fainelli <f.fainelli@...il.com>,
        bcm-kernel-feedback-list@...adcom.com, james.quinlan@...adcom.com,
        mbrugger@...e.com, phil@...pberrypi.org, jeremy.linton@....com,
        linux-pci@...r.kernel.org, linux-rpi-kernel@...ts.infradead.org,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v3 5/7] PCI: brcmstb: add MSI capability

On Tue, Nov 26, 2019 at 10:19:43AM +0100, Nicolas Saenz Julienne wrote:
> From: Jim Quinlan <james.quinlan@...adcom.com>
> 
> This adds MSI support to the Broadcom STB PCIe host controller. The MSI
> controller is physically located within the PCIe block, however, there
> is no reason why the MSI controller could not be moved elsewhere in the
> future. MSIX is not supported by the HW.
> 
> Since the internal Brcmstb MSI controller is intertwined with the PCIe
> controller, it is not its own platform device but rather part of the
> PCIe platform device.
> 
> Signed-off-by: Jim Quinlan <james.quinlan@...adcom.com>
> Co-developed-by: Nicolas Saenz Julienne <nsaenzjulienne@...e.de>
> Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@...e.de>
> Reviewed-by: Marc Zyngier <maz@...nel.org>
> 
> ---
> 
> Changes since v2 (kept Marc's Reviewed-by as changes didn't affect irq
> subsystem stuff or seem petty enough):
>   - Use standard APIs on register operations
>   - Get rid of revision code

Do any RPI4's have a HW revision of less than 33?


>   - Update rules to msi_target_addr selection
>   - Remove unwarranted MSI_FLAG_PCI_MSIX
>   - Small cosmetic changes
> 
> Changes since v1:
>   - Move revision code and some registers to this patch
>   - Use PCIE_MSI_IRQ_DOMAIN in Kconfig
>   - Remove redundant register read from ISR
>   - Fail probe on MSI init error
>   - Get rid of msi_internal
>   - Use bitmap family of functions
>   - Use edge triggered setup
>   - Add comment regarding MultiMSI
>   - Simplify compose_msi_msg to avoid reg read
> 
> This is based on Jim's original submission[1] with some slight changes
> regarding how pcie->msi_target_addr is decided.
> 
> [1] https://patchwork.kernel.org/patch/10605955/
> 
>  drivers/pci/controller/Kconfig        |   1 +
>  drivers/pci/controller/pcie-brcmstb.c | 261 +++++++++++++++++++++++++-
>  2 files changed, 261 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> index 27504f108ee5..918e283bbff1 100644


> +
> +static void brcm_msi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
> +{
> +	struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
> +
> +	msg->address_lo = lower_32_bits(msi->target_addr);
> +	msg->address_hi = upper_32_bits(msi->target_addr);
> +	msg->data = 0x6540 | data->hwirq;

NIT: Perhaps this 0x6540 can be a define - just in the same way we have a define
for PCIE_MISC_MSI_DATA_CONFIG_VAL.

Thanks,

Andrew Murray

> +}
> +
> -- 
> 2.24.0
>