linux-kernel - [PATCH 5.3 005/135] clk: meson: gxbb: let sar_adc_clk

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Message-Id: <20191203213006.733032204@linuxfoundation.org>
Date:   Tue,  3 Dec 2019 23:34:05 +0100
From:   Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To:     linux-kernel@...r.kernel.org
Cc:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        stable@...r.kernel.org,
        Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
        Jerome Brunet <jbrunet@...libre.com>,
        Sasha Levin <sashal@...nel.org>
Subject: [PATCH 5.3 005/135] clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate

From: Martin Blumenstingl <martin.blumenstingl@...glemail.com>

[ Upstream commit 44b09b11b813b8550e6b976ea51593bc23bba8d1 ]

The meson-saradc driver manually sets the input clock for
sar_adc_clk_sel. Update the GXBB clock driver (which is used on GXBB,
GXL and GXM) so the rate settings on sar_adc_clk_div are propagated up
to sar_adc_clk_sel which will let the common clock framework select the
best matching parent clock if we want that.

This makes sar_adc_clk_div consistent with the axg-aoclk and g12a-aoclk
drivers, which both also specify CLK_SET_RATE_PARENT.

Fixes: 33d0fcdfe0e870 ("clk: gxbb: add the SAR ADC clocks and expose them")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Signed-off-by: Jerome Brunet <jbrunet@...libre.com>
Signed-off-by: Sasha Levin <sashal@...nel.org>
---
 drivers/clk/meson/gxbb.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index dab16d9b1af8b..9834eb2c1b674 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -866,6 +866,7 @@ static struct clk_regmap gxbb_sar_adc_clk_div = {
 		.ops = &clk_regmap_divider_ops,
 		.parent_names = (const char *[]){ "sar_adc_clk_sel" },
 		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
-- 
2.20.1