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Message-ID: <dd0d91b74853d1afa9bcb8a56a3ddbfa744ae116.camel@suse.de>
Date: Tue, 03 Dec 2019 18:23:03 +0100
From: Nicolas Saenz Julienne <nsaenzjulienne@...e.de>
To: Jeremy Linton <jeremy.linton@....com>, andrew.murray@....com,
maz@...nel.org, linux-kernel@...r.kernel.org,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Eric Anholt <eric@...olt.net>,
Stefan Wahren <wahrenst@....net>,
Florian Fainelli <f.fainelli@...il.com>,
bcm-kernel-feedback-list@...adcom.com
Cc: james.quinlan@...adcom.com, mbrugger@...e.com,
phil@...pberrypi.org, linux-pci@...r.kernel.org,
linux-rpi-kernel@...ts.infradead.org,
Bjorn Helgaas <bhelgaas@...gle.com>,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v3 4/7] PCI: brcmstb: add Broadcom STB PCIe host
controller driver
On Tue, 2019-12-03 at 10:31 -0600, Jeremy Linton wrote:
> Hi,
>
> On 11/26/19 3:19 AM, Nicolas Saenz Julienne wrote:
> > From: Jim Quinlan <james.quinlan@...adcom.com>
> >
> > This adds a basic driver for Broadcom's STB PCIe controller, for now
> > aimed at Raspberry Pi 4's SoC, bcm2711.
> >
> > Signed-off-by: Jim Quinlan <james.quinlan@...adcom.com>
> > Co-developed-by: Nicolas Saenz Julienne <nsaenzjulienne@...e.de>
> > Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@...e.de>
> >
> > ---
> >
> > Changes since v2:
> > - Correct rc_bar2_offset sign
> > - Invert IRQ clear and masking in setup code
> > - Use bitfield.h, redo all register ops while keeping the register
> > names intact
> > - Remove all SHIFT register definitions
> > - Get rid of all _RB writes
> > - Get rid of of_data
> > - Don't iterate over inexisting dma-ranges
> > - Add comment regarding dma-ranges validation
> > - Small cosmetic cleanups
> > - Fix license mismatch
> > - Set driver Kconfig tristate
> > - Didn't add any comment about the controller not being I/O coherent
> > for now as I wait for Jeremy's reply
>
> I guess its fine.. In answer to the original query. It seems that this
> PCIe bridge requires explicit cache operations for DMA from PCIe
> endpoints. This wasn't obvious to me at first reading because I was
> assuming the custom DMA ops were strictly to deal with the stated DMA
> limits.
Thanks, I now see what you meant.
> So if you end up respinning, it still might be worthy mentioning
> somewhere that this is a non-coherent PCIe implementation. I still hold
> much of my original reservations about pieces of this driver.
> Particularly, how it might look if someone wanted to boot the RPi using
> ACPI on linux. But, I was shown a clever bit of AML recently, which
> solves those problems for the RPi and the attached XHCI.
I don't know much about ACPI, but ultimately if you're booting trough ACPI,
you're unlikely to use device-tree at all, right? And if you where and this
driver clashed with your ACPI implementation you'd simply have to disable it on
the device-tree.
> So, given how much time I've looked at the root port configuration/etc
> sections of this driver and I've not found a serious bug:
>
> Reviewed-by: Jeremy Linton <jeremy.linton@....com>
Thanks!
Regards,
Nicolas
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