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Date: Wed, 4 Dec 2019 14:25:38 -0800
From: Matthias Kaehlcke <mka@...omium.org>
To: Veerabhadrarao Badiganti <vbadigan@...eaurora.org>
Cc: adrian.hunter@...el.com, ulf.hansson@...aro.org,
robh+dt@...nel.org, asutoshd@...eaurora.org,
stummala@...eaurora.org, sayalil@...eaurora.org,
cang@...eaurora.org, rampraka@...eaurora.org,
linux-mmc@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
Andy Gross <agross@...nel.org>,
Mark Rutland <mark.rutland@....com>
Subject: Re: [PATCH V1 2/2] arm64: dts: qcom: sc7180: Add nodes for eMMC and
SD card
Hi,
On Wed, Nov 27, 2019 at 11:50:06AM +0000, Veerabhadrarao Badiganti wrote:
> Add sdhc instances for supporting eMMC and SD-card on sc7180.
> The regulators should be in HPM state for proper functionality of
> eMMC and SD-card. Updating corresponding regulators accordingly.
>
> Signed-off-by: Veerabhadrarao Badiganti <vbadigan@...eaurora.org>
> ---
>
> This depends on the patch series (dt support for sc7180):
> https://lkml.org/lkml/2019/11/8/149
> ---
> arch/arm64/boot/dts/qcom/sc7180-idp.dts | 32 +++++++-
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 136 ++++++++++++++++++++++++++++++++
> 2 files changed, 164 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> index 189254f..583c42c 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> @@ -11,6 +11,7 @@
> #include "sc7180.dtsi"
> #include "pm6150.dtsi"
> #include "pm6150l.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
I think this should be above, together with
'dt-bindings/regulator/qcom,rpmh-regulator.h'
>
> / {
> model = "Qualcomm Technologies, Inc. SC7180 IDP";
> @@ -103,7 +104,7 @@
> vreg_l12a_1p8: ldo12 {
> regulator-min-microvolt = <1696000>;
> regulator-max-microvolt = <1952000>;
> - regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> };
>
> vreg_l13a_1p8: ldo13 {
> @@ -145,7 +146,7 @@
> vreg_l19a_2p9: ldo19 {
> regulator-min-microvolt = <2696000>;
> regulator-max-microvolt = <3304000>;
> - regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> };
> };
>
> @@ -191,7 +192,7 @@
> vreg_l6c_2p9: ldo6 {
> regulator-min-microvolt = <2696000>;
> regulator-max-microvolt = <3304000>;
> - regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> };
>
> vreg_l7c_3p0: ldo7 {
> @@ -209,7 +210,7 @@
> vreg_l9c_2p9: ldo9 {
> regulator-min-microvolt = <2952000>;
> regulator-max-microvolt = <3304000>;
> - regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> };
>
> vreg_l10c_3p3: ldo10 {
> @@ -400,3 +401,26 @@
> bias-pull-up;
> };
> };
> +
> +&sdhc_1 {
> + status = "ok";
> +
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&sdc1_on>;
> + pinctrl-1 = <&sdc1_off>;
> + vmmc-supply = <&vreg_l19a_2p9>;
> + vqmmc-supply = <&vreg_l12a_1p8>;
> +
remove empty line
> +};
> +
> +&sdhc_2 {
> + status = "ok";
> +
> + pinctrl-names = "default","sleep";
> + pinctrl-0 = <&sdc2_on>;
> + pinctrl-1 = <&sdc2_off>;
> + vmmc-supply = <&vreg_l9c_2p9>;
> + vqmmc-supply = <&vreg_l6c_2p9>;
> +
> + cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>;
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 666e9b9..207d44f 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -897,6 +897,100 @@
> function = "qup15";
> };
> };
> +
> + sdc1_on: sdc1-on {
> + clk {
> + pins = "sdc1_clk";
> + bias-disable;
> + drive-strength = <16>;
> + };
> +
> + cmd {
> + pins = "sdc1_cmd";
> + bias-pull-up;
> + drive-strength = <10>;
> + };
> +
> + data {
> + pins = "sdc1_data";
> + bias-pull-up;
> + drive-strength = <10>;
> + };
> +
> + rclk {
> + pins = "sdc1_rclk";
> + bias-pull-down;
> + };
> + };
> +
> + sdc1_off: sdc1-off {
> + clk {
> + pins = "sdc1_clk";
> + bias-disable;
> + drive-strength = <2>;
> + };
> +
> + cmd {
> + pins = "sdc1_cmd";
> + bias-pull-up;
> + drive-strength = <2>;
> + };
> +
> + data {
> + pins = "sdc1_data";
> + bias-pull-up;
> + drive-strength = <2>;
> + };
> +
> + rclk {
> + pins = "sdc1_rclk";
> + bias-pull-down;
> + };
> + };
> +
> + sdc2_on: sdc2_on {
> + clk {
> + pins = "sdc2_clk";
> + bias-disable;
> + drive-strength = <16>;
> + };
nit: add blank lines, consistent with the other pinconf entries.
> + cmd {
> + pins = "sdc2_cmd";
> + bias-pull-up;
> + drive-strength = <10>;
> + };
> + data {
> + pins = "sdc2_data";
> + bias-pull-up;
> + drive-strength = <10>;
> + };
> + sd-cd {
> + pins = "gpio69";
> + bias-pull-down;
> + };
> + };
> +
> + sdc2_off: sdc2_off {
> + clk {
> + pins = "sdc2_clk";
> + bias-disable;
> + drive-strength = <2>;
> + };
> + cmd {
> + pins = "sdc2_cmd";
> + bias-pull-up;
> + drive-strength = <2>;
> + };
> + data {
> + pins = "sdc2_data";
> + bias-pull-up;
> + drive-strength = <2>;
> + };
> + sd-cd {
> + pins = "gpio69";
> + bias-pull-down;
> + };
> + };
> };
>
> qspi: spi@...c000 {
> @@ -911,6 +1005,48 @@
> status = "disabled";
> };
>
> + sdhc_1: sdhci@...000 {
IIUC the nodes are ordered by address, hence this one should be between
'clock-controller@...000' and 'geniqup@...000'.
> + compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
> + reg = <0 0x7c4000 0 0x1000>;
> + reg-names = "hc_mem";
> +
> + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq", "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC1_APPS_CLK>,
> + <&gcc GCC_SDCC1_AHB_CLK>;
> + clock-names = "core", "iface";
> +
> + bus-width = <8>;
> + non-removable;
> +
> + mmc-ddr-1_8v;
> + mmc-hs200-1_8v;
> + mmc-hs400-1_8v;
> + mmc-hs400-enhanced-strobe;
> +
> + status = "disabled";
> + };
> +
> + sdhc_2: sdhci@...4000 {
nodes are ordered by address: this one should be between 'pinctrl@...0000'
and 'spi@...c000ยด.
> + compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
> + reg = <0 0x08804000 0 0x1000>;
> + reg-names = "hc_mem";
> +
> + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq", "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC2_APPS_CLK>,
> + <&gcc GCC_SDCC2_AHB_CLK>;
> + clock-names = "core","iface";
nit: add a blank after the comma.
Thanks
Matthias
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