[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <DB7PR04MB4490FBD7321BD39AE83E37D68F5D0@DB7PR04MB4490.eurprd04.prod.outlook.com>
Date: Wed, 4 Dec 2019 03:07:29 +0000
From: Biwen Li <biwen.li@....com>
To: Biwen Li <biwen.li@....com>, Leo Li <leoyang.li@....com>,
"shawnguo@...nel.org" <shawnguo@...nel.org>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
"mark.rutland@....com" <mark.rutland@....com>,
Ran Wang <ran.wang_1@....com>
CC: "linuxppc-dev@...ts.ozlabs.org" <linuxppc-dev@...ts.ozlabs.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Subject: RE: [v5 1/3] soc: fsl: handle RCPM errata A-008646 on SoC LS1021A
Hi All,
1.Need apply below patches before apply these patches.
1.1 Flextimer dts
https://lore.kernel.org/patchwork/series/405653/mbox/ (https://lore.kernel.org/patchwork/patch/1112493/)
1.2 RCPM driver
https://lore.kernel.org/patchwork/patch/1143809/mbox/ [v10,1/3] PM: wakeup: Add routine to help fetch wakeup source object)
https://lore.kernel.org/patchwork/patch/1143810/mbox/ ([v10,2/3] Documentation: dt: binding: fsl: Add 'little-endian' and update Chassis define)
https://lore.kernel.org/patchwork/patch/1143811/mbox/ ([v10,3/3] soc: fsl: add RCPM driver)
> Subject: [v5 1/3] soc: fsl: handle RCPM errata A-008646 on SoC LS1021A
>
> Description:
> - Reading configuration register RCPM_IPPDEXPCR1
> always return zero
>
> Workaround:
> - Save register RCPM_IPPDEXPCR1's value to
> register SCFG_SPARECR8.(uboot's psci also
> need reading value from the register SCFG_SPARECR8
> to set register RCPM_IPPDEXPCR1)
>
> Impact:
> - FlexTimer module will cannot wakeup system in
> deep sleep on SoC LS1021A
>
> Signed-off-by: Biwen Li <biwen.li@....com>
> ---
> Change in v5:
> - update the patch, because of rcpm driver has updated.
>
> Change in v4:
> - rename property name
> fsl,ippdexpcr-alt-addr -> fsl,ippdexpcr1-alt-addr
>
> Change in v3:
> - update commit message
> - rename property name
> fsl,rcpm-scfg -> fsl,ippdexpcr-alt-addr
>
> Change in v2:
> - fix stype problems
>
> drivers/soc/fsl/rcpm.c | 47
> ++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 45 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/soc/fsl/rcpm.c b/drivers/soc/fsl/rcpm.c index
> a093dbe6d2cb..775c618f0456 100644
> --- a/drivers/soc/fsl/rcpm.c
> +++ b/drivers/soc/fsl/rcpm.c
> @@ -6,13 +6,16 @@
> //
> // Author: Ran Wang <ran.wang_1@....com>
>
> +#include <linux/acpi.h>
> #include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> #include <linux/module.h>
> -#include <linux/platform_device.h>
> #include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> #include <linux/slab.h>
> #include <linux/suspend.h>
> -#include <linux/kernel.h>
>
> #define RCPM_WAKEUP_CELL_MAX_SIZE 7
>
> @@ -37,6 +40,9 @@ static int rcpm_pm_prepare(struct device *dev)
> struct device_node *np = dev->of_node;
> u32 value[RCPM_WAKEUP_CELL_MAX_SIZE + 1];
> u32 setting[RCPM_WAKEUP_CELL_MAX_SIZE] = {0};
> + struct regmap *scfg_addr_regmap = NULL;
> + u32 reg_offset[RCPM_WAKEUP_CELL_MAX_SIZE + 1];
> + u32 reg_value = 0;
>
> rcpm = dev_get_drvdata(dev);
> if (!rcpm)
> @@ -90,6 +96,43 @@ static int rcpm_pm_prepare(struct device *dev)
> tmp |= ioread32be(address);
> iowrite32be(tmp, address);
> }
> + /*
> + * Workaround of errata A-008646 on SoC LS1021A:
> + * There is a bug of register ippdexpcr1.
> + * Reading configuration register RCPM_IPPDEXPCR1
> + * always return zero. So save ippdexpcr1's value
> + * to register SCFG_SPARECR8.And the value of
> + * ippdexpcr1 will be read from SCFG_SPARECR8.
> + */
> + if (device_property_present(dev, "fsl,ippdexpcr1-alt-addr")) {
> + if (dev_of_node(dev)) {
> + scfg_addr_regmap =
> syscon_regmap_lookup_by_phandle(np,
> +
> "fsl,ippdexpcr1-alt-addr");
> + } else if (is_acpi_node(dev->fwnode)) {
> + dev_err(dev, "not support acpi for rcpm\n");
> + continue;
> + }
> +
> + if (scfg_addr_regmap && (i == 1)) {
> + if (device_property_read_u32_array(dev,
> + "fsl,ippdexpcr1-alt-addr",
> + reg_offset,
> + 1 + sizeof(u64)/sizeof(u32))) {
> + scfg_addr_regmap = NULL;
> + continue;
> + }
> + /* Read value from register SCFG_SPARECR8 */
> + regmap_read(scfg_addr_regmap,
> + (u32)(((u64)(reg_offset[1] << (sizeof(u32) * 8) |
> + reg_offset[2])) & 0xffffffff),
> + ®_value);
> + /* Write value to register SCFG_SPARECR8 */
> + regmap_write(scfg_addr_regmap,
> + (u32)(((u64)(reg_offset[1] << (sizeof(u32) * 8) |
> + reg_offset[2])) & 0xffffffff),
> + tmp | reg_value);
> + }
> + }
> }
>
> return 0;
> --
> 2.17.1
Powered by blists - more mailing lists