linux-kernel - RE: [EXT] Re: [v11 1/2] dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings

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Date:   Fri, 6 Dec 2019 03:01:44 +0000
From:   Wen He <wen.he_1@....com>
To:     Rob Herring <robh@...nel.org>
CC:     Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Michael Walle <michael@...le.cc>, Leo Li <leoyang.li@....com>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [EXT] Re: [v11 1/2] dt/bindings: clk: Add YAML schemas for
 LS1028A Display Clock bindings



> -----Original Message-----
> From: Rob Herring <robh@...nel.org>
> Sent: 2019年12月5日 22:27
> To: Wen He <wen.he_1@....com>
> Cc: Michael Turquette <mturquette@...libre.com>; Stephen Boyd
> <sboyd@...nel.org>; Mark Rutland <mark.rutland@....com>; Michael Walle
> <michael@...le.cc>; Leo Li <leoyang.li@....com>;
> devicetree@...r.kernel.org; linux-clk@...r.kernel.org;
> linux-kernel@...r.kernel.org
> Subject: [EXT] Re: [v11 1/2] dt/bindings: clk: Add YAML schemas for LS1028A
> Display Clock bindings
> 
> Caution: EXT Email
> 
> On Thu, Dec 05, 2019 at 03:26:52PM +0800, Wen He wrote:
> > LS1028A has a clock domain PXLCLK0 used for provide pixel clocks to
> > Display output interface. Add a YAML schema for this.
> >
> > Signed-off-by: Wen He <wen.he_1@....com>
> > Signed-off-by: Michael Walle <michael@...le.cc>
> > ---
> > change in v11:
> >       - renamed 'vco-frequency' to 'fsl,vco-hz' to clearly feild
> > definiation
> >
> >  .../devicetree/bindings/clock/fsl,plldig.yaml | 55
> > +++++++++++++++++++
> >  1 file changed, 55 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/clock/fsl,plldig.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/clock/fsl,plldig.yaml
> > b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml
> > new file mode 100644
> > index 000000000000..23cce65b3a93
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml
> > @@ -0,0 +1,55 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +%YAML 1.2
> > +---
> > +$id:
> > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> >
> +cetree.org%2Fschemas%2Fbindings%2Fclock%2Ffsl%2Cplldig.yaml%23&amp;
> da
> >
> +ta=02%7C01%7Cwen.he_1%40nxp.com%7Cbc3e7eabcfef4f75316e08d7798f
> 2c2e%7C
> >
> +686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63711152813315072
> 4&amp;sda
> >
> +ta=vFRvWaWgdyIWqQAVE7NXnUKCnE%2BU38svA%2BjWqNc%2Fb8w%3D&a
> mp;reserved=
> > +0
> > +$schema:
> > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> >
> +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&amp;data=02%7C01%7Cwen
> .he_1%
> >
> +40nxp.com%7Cbc3e7eabcfef4f75316e08d7798f2c2e%7C686ea1d3bc2b4c6f
> a92cd9
> >
> +9c5c301635%7C0%7C0%7C637111528133150724&amp;sdata=dqj%2FBK%2
> F4%2BBmfk
> > +HkGjeNZm3FZZlTYPJOzEKroyH0jKDA%3D&amp;reserved=0
> > +
> > +title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding
> > +
> > +maintainers:
> > +  - Wen He <wen.he_1@....com>
> > +
> > +description: |
> > +  NXP LS1028A has a clock domain PXLCLK0 used for the Display output
> > +  interface in the display core, as implemented in TSMC CLN28HPM PLL.
> > +  which generate and offers pixel clocks to Display.
> > +
> > +properties:
> > +  compatible:
> > +    const: fsl,ls1028a-plldig
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  '#clock-cells':
> > +    const: 0
> > +
> > +  fsl,vco-hz:
> > +     $ref: '/schemas/types.yaml#/definitions/uint32'
> 
> Drop this as '*-hz' already has a type.
> 
> With that,
> 
> Reviewed-by: Rob Herring <robh@...nel.org>

Thanks a lot; 

Best Regards,
Wen

> 
> > +     description: Optional for VCO frequency of the PLL in Hertz.
> > +        The VCO frequency of this PLL cannot be changed during runtime
> > +        only at startup. Therefore, the output frequencies are very
> > +        limited and might not even closely match the requested
> frequency.
> > +        To work around this restriction the user may specify its own
> > +        desired VCO frequency for the PLL.
> > +     minimum: 650000000
> > +     maximum: 1300000000
> > +     default: 1188000000
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +  - '#clock-cells'
> > +
> > +examples:
> > +  # Display PIXEL Clock node:
> > +  - |
> > +    dpclk: clock-display@...0000 {
> > +        compatible = "fsl,ls1028a-plldig";
> > +        reg = <0x0 0xf1f0000 0x0 0xffff>;
> > +        #clock-cells = <0>;
> > +        clocks = <&osc_27m>;
> > +    };
> > +
> > +...
> > --
> > 2.17.1
> >