linux-kernel - [PATCH 0/2] L2 ccache DT and cacheinfo support to read no. of L2 cache ways enabled

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Message-Id: <1575890706-36162-1-git-send-email-yash.shah@sifive.com>
Date:   Mon,  9 Dec 2019 16:55:04 +0530
From:   Yash Shah <yash.shah@...ive.com>
To:     robh+dt@...nel.org, mark.rutland@....com, paul.walmsley@...ive.com
Cc:     palmer@...belt.com, aou@...s.berkeley.edu, bmeng.cn@...il.com,
        allison@...utok.net, alexios.zavras@...el.com, atish.patra@....com,
        tglx@...utronix.de, gregkh@...uxfoundation.org,
        devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
        linux-kernel@...r.kernel.org, Yash Shah <yash.shah@...ive.com>
Subject: [PATCH 0/2] L2 ccache DT and cacheinfo support to read no. of L2 cache ways enabled

The patchset includes the patch to implement a private attribute named
"number_of_ways_enabled" in the cacheinfo framework. Reading this
attribute returns the number of L2 cache ways enabled at runtime,
The patchset also include the patch to add DT node for SiFive L2 cache
controller.

This patchset is based on Linux v5.4 and tested on HiFive Unleashed
board. The cacheinfo patch depends on Christoph Hellwig's patch:
"riscv: move sifive_l2_cache.c to drivers/soc"

Yash Shah (2):
  riscv: dts: Add DT support for SiFive L2 cache controller
  riscv: cacheinfo: Add support to determine no. of L2 cache way enabled

 arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 26 +++++++++++++++++++++++++
 arch/riscv/include/asm/sifive_l2_cache.h   |  2 ++
 arch/riscv/kernel/cacheinfo.c              | 31 ++++++++++++++++++++++++++++++
 drivers/soc/sifive/sifive_l2_cache.c       |  5 +++++
 4 files changed, 64 insertions(+)

-- 
2.7.4