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Message-ID: <20191209211554.GA217130@google.com>
Date: Mon, 9 Dec 2019 15:15:54 -0600
From: Bjorn Helgaas <helgaas@...nel.org>
To: Kishon Vijay Abraham I <kishon@...com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Rob Herring <robh+dt@...nel.org>,
Arnd Bergmann <arnd@...db.de>,
Andrew Murray <andrew.murray@....com>,
linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-omap@...r.kernel.org
Subject: Re: [PATCH 05/13] PCI: cadence: Add read and write accessors to
perform only 32-bit accesses
On Mon, Dec 09, 2019 at 02:51:39PM +0530, Kishon Vijay Abraham I wrote:
> Certain platforms like TI's J721E allow only 32-bit register accesses.
> Add read and write accessors to perform only 32-bit accesses in order to
> support platfroms like TI's J721E.
s/platfroms/platforms/
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