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Message-Id: <20191210200014.949529-1-arnd@arndb.de>
Date: Tue, 10 Dec 2019 20:59:55 +0100
From: Arnd Bergmann <arnd@...db.de>
To: Piotr Sroka <piotrs@...ence.com>,
Miquel Raynal <miquel.raynal@...tlin.com>,
Richard Weinberger <richard@....at>,
Vignesh Raghavendra <vigneshr@...com>
Cc: Arnd Bergmann <arnd@...db.de>, kbuild test robot <lkp@...el.com>,
Julia Lawall <julia.lawall@...6.fr>,
YueHaibing <yuehaibing@...wei.com>,
linux-mtd@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [PATCH] mtd: rawnand: cadence: fix address space mixup
dma_addr_t and pointers can are not interchangeable, and can
be different sizes:
drivers/mtd/nand/raw/cadence-nand-controller.c: In function 'cadence_nand_cdma_transfer':
drivers/mtd/nand/raw/cadence-nand-controller.c:1283:12: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast]
(void *)dma_buf, (void *)dma_ctrl_dat,
^
drivers/mtd/nand/raw/cadence-nand-controller.c:1283:29: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast]
(void *)dma_buf, (void *)dma_ctrl_dat,
^
Use dma_addr_t consistently here, which cleans up a couple of casts
as a side-effect.
Fixes: ec4ba01e894d ("mtd: rawnand: Add new Cadence NAND driver to MTD subsystem")
Signed-off-by: Arnd Bergmann <arnd@...db.de>
---
.../mtd/nand/raw/cadence-nand-controller.c | 21 ++++++++-----------
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/nand/raw/cadence-nand-controller.c b/drivers/mtd/nand/raw/cadence-nand-controller.c
index 3a36285a8d8a..5a2d7e7ffaee 100644
--- a/drivers/mtd/nand/raw/cadence-nand-controller.c
+++ b/drivers/mtd/nand/raw/cadence-nand-controller.c
@@ -402,7 +402,7 @@ struct cadence_nand_cdma_desc {
u16 rsvd2;
/* System/host memory address required for data DMA commands. */
- u64 memory_pointer;
+ u64 memory_addr;
/* Status of operation. */
u32 status;
@@ -416,7 +416,7 @@ struct cadence_nand_cdma_desc {
u32 rsvd4;
/* Control data pointer. */
- u64 ctrl_data_ptr;
+ u64 ctrl_data_addr;
};
/* Interrupt status. */
@@ -914,8 +914,8 @@ static void cadence_nand_get_caps(struct cdns_nand_ctrl *cdns_ctrl)
/* Prepare CDMA descriptor. */
static void
cadence_nand_cdma_desc_prepare(struct cdns_nand_ctrl *cdns_ctrl,
- char nf_mem, u32 flash_ptr, char *mem_ptr,
- char *ctrl_data_ptr, u16 ctype)
+ char nf_mem, u32 flash_ptr, dma_addr_t mem_addr,
+ dma_addr_t ctrl_data_addr, u16 ctype)
{
struct cadence_nand_cdma_desc *cdma_desc = cdns_ctrl->cdma_desc;
@@ -931,13 +931,13 @@ cadence_nand_cdma_desc_prepare(struct cdns_nand_ctrl *cdns_ctrl,
cdma_desc->command_flags |= CDMA_CF_DMA_MASTER;
cdma_desc->command_flags |= CDMA_CF_INT;
- cdma_desc->memory_pointer = (uintptr_t)mem_ptr;
+ cdma_desc->memory_addr = mem_addr;
cdma_desc->status = 0;
cdma_desc->sync_flag_pointer = 0;
cdma_desc->sync_arguments = 0;
cdma_desc->command_type = ctype;
- cdma_desc->ctrl_data_ptr = (uintptr_t)ctrl_data_ptr;
+ cdma_desc->ctrl_data_addr = ctrl_data_addr;
}
static u8 cadence_nand_check_desc_error(struct cdns_nand_ctrl *cdns_ctrl,
@@ -1280,8 +1280,7 @@ cadence_nand_cdma_transfer(struct cdns_nand_ctrl *cdns_ctrl, u8 chip_nr,
}
cadence_nand_cdma_desc_prepare(cdns_ctrl, chip_nr, page,
- (void *)dma_buf, (void *)dma_ctrl_dat,
- ctype);
+ dma_buf, dma_ctrl_dat, ctype);
status = cadence_nand_cdma_send_and_wait(cdns_ctrl, thread_nr);
@@ -1358,10 +1357,8 @@ static int cadence_nand_erase(struct nand_chip *chip, u32 page)
int status;
u8 thread_nr = cdns_chip->cs[chip->cur_cs];
- cadence_nand_cdma_desc_prepare(cdns_ctrl,
- cdns_chip->cs[chip->cur_cs],
- page, NULL, NULL,
- CDMA_CT_ERASE);
+ cadence_nand_cdma_desc_prepare(cdns_ctrl, cdns_chip->cs[chip->cur_cs],
+ page, 0, 0, CDMA_CT_ERASE);
status = cadence_nand_cdma_send_and_wait(cdns_ctrl, thread_nr);
if (status) {
dev_err(cdns_ctrl->dev, "erase operation failed\n");
--
2.20.0
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