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Date:   Tue, 10 Dec 2019 14:55:03 -0800
From:   Paul Burton <paulburton@...nel.org>
To:     Paul Cercueil <paul@...pouillou.net>,
        Zhou Yanjie <zhouyanjie@...o.com>
Cc:     linux-mips@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
        robh+dt@...nel.org, paul.burton@...s.com, mturquette@...libre.com,
        sboyd@...nel.org, mark.rutland@....com, syq@...ian.org,
        sernia.zhou@...mail.com, zhenwenjin@...il.com
Subject: Re: [PATCH 1/5] clk: Ingenic: Adjust code to make it compatible with
 X1830.

Hi Paul, Zhou,

On Fri, Nov 29, 2019 at 12:23:42PM +0100, Paul Cercueil wrote:
> > > > @@ -93,8 +93,17 @@ ingenic_pll_recalc_rate(struct clk_hw *hw,
> > > > unsigned long parent_rate)
> > > >      n += pll_info->n_offset;
> > > >      od_enc = ctl >> pll_info->od_shift;
> > > >      od_enc &= GENMASK(pll_info->od_bits - 1, 0);
> > > > -    bypass = !pll_info->no_bypass_bit &&
> > > > -         !!(ctl & BIT(pll_info->bypass_bit));
> > > > +
> > > > +    if (pll_info->version >= CGU_X1830) {
> > > > +        spin_lock_irqsave(&cgu->lock, flags);
> > > > +        ctl = readl(cgu->base + pll_info->reg[0]);
> > > > +        spin_unlock_irqrestore(&cgu->lock, flags);
> > > 
> > > Why the spinlock?
> > > 
> > 
> > The original code used spinlock when reading the control register,
> > so when reading this new control register, I think it should also
> > be added with spinlock.
> 
> Well, the original code looks wrong to me. There's nothing to protect here.
> 
> Maybe @Paul Burton can shed some light?

I wish I could remember, but I agree it seems pointless here. The only
way I can think it could be of any use is if writes to the CGU register
we're accessing aren't atomic (ie. if we could observe a partially
completed write), but I don't believe that's the case.

So Zhou, if you want to drop the spinlock here from your X1830 path &
ideally also add a patch to remove it in the non-X1830 path that would
be great.

Thanks,
    Paul

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