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Message-Id: <20191211150350.722636762@linuxfoundation.org>
Date: Wed, 11 Dec 2019 16:05:33 +0100
From: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To: linux-kernel@...r.kernel.org
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
stable@...r.kernel.org,
Takeshi Kihara <takeshi.kihara.df@...esas.com>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Stephen Boyd <sboyd@...nel.org>,
Laurent Pinchart <laurent.pinchart@...asonboard.com>,
Sasha Levin <sashal@...nel.org>
Subject: [PATCH 4.19 171/243] clk: renesas: r8a77990: Correct parent clock of DU
From: Takeshi Kihara <takeshi.kihara.df@...esas.com>
[ Upstream commit 7cf3a216a2b3a672cad3e498c186c9333bdff90a ]
According to the R-Car Gen3 Hardware Manual Rev 1.00, the parent clock
of the DU module clocks on R-Car E3 is S1D1.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@...esas.com>
Fixes: 3570a2af473789c5 ("clk: renesas: cpg-mssr: Add support for R-Car E3")
Signed-off-by: Geert Uytterhoeven <geert+renesas@...der.be>
Acked-by: Stephen Boyd <sboyd@...nel.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@...asonboard.com>
Signed-off-by: Sasha Levin <sashal@...nel.org>
---
drivers/clk/renesas/r8a77990-cpg-mssr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index 9e14f1486fbb9..81569767025cc 100644
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -175,8 +175,8 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
DEF_MOD("ehci0", 703, R8A77990_CLK_S3D4),
DEF_MOD("hsusb", 704, R8A77990_CLK_S3D4),
DEF_MOD("csi40", 716, R8A77990_CLK_CSI0),
- DEF_MOD("du1", 723, R8A77990_CLK_S2D1),
- DEF_MOD("du0", 724, R8A77990_CLK_S2D1),
+ DEF_MOD("du1", 723, R8A77990_CLK_S1D1),
+ DEF_MOD("du0", 724, R8A77990_CLK_S1D1),
DEF_MOD("lvds", 727, R8A77990_CLK_S2D1),
DEF_MOD("vin5", 806, R8A77990_CLK_S1D2),
--
2.20.1
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