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Message-ID: <f58c3ae0-9807-bea8-4570-28d975336090@huawei.com>
Date: Wed, 11 Dec 2019 09:41:05 +0000
From: John Garry <john.garry@...wei.com>
To: Marc Zyngier <maz@...nel.org>
CC: Ming Lei <ming.lei@...hat.com>,
"tglx@...utronix.de" <tglx@...utronix.de>,
"chenxiang (M)" <chenxiang66@...ilicon.com>,
"bigeasy@...utronix.de" <bigeasy@...utronix.de>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"hare@...e.com" <hare@...e.com>, "hch@....de" <hch@....de>,
"axboe@...nel.dk" <axboe@...nel.dk>,
"bvanassche@....org" <bvanassche@....org>,
"peterz@...radead.org" <peterz@...radead.org>,
"mingo@...hat.com" <mingo@...hat.com>
Subject: Re: [PATCH RFC 1/1] genirq: Make threaded handler use irq affinity
for managed interrupt
On 10/12/2019 18:32, Marc Zyngier wrote:
>>>> The ITS code will make the lowest online CPU in the affinity mask
>>>> the
>>>> target CPU for the interrupt, which may result in some CPUs
>>>> handling
>>>> so many interrupts.
>>> If what you want is for the*default* affinity to be spread around,
>>> that should be achieved pretty easily. Let me have a think about how
>>> to do that.
>> Cool, I anticipate that it should help my case.
>>
>> I can also seek out some NVMe cards to see how it would help a more
>> "generic" scenario.
> Can you give the following a go? It probably has all kind of warts on
> top of the quality debug information, but I managed to get my D05 and
> a couple of guests to boot with it. It will probably eat your data,
> so use caution!;-)
>
Hi Marc,
Ok, we'll give it a spin.
Thanks,
John
> Thanks,
>
> M.
>
> diff --git a/drivers/irqchip/irq-gic-v3-its.c
> b/drivers/irqchip/irq-gic-v3-its.c
> index e05673bcd52b..301ee3bc0602 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -177,6 +177,8 @@ static DEFINE_IDA(its_vpeid_ida);
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