Message-ID: <d092bae0-69ea-0a57-4db5-6de074956564@intel.com>
Date:   Wed, 11 Dec 2019 06:13:36 -0800
From:   Dave Hansen <dave.hansen@...el.com>
To:     Suravee Suthikulpanit <suravee.suthikulpanit@....com>,
        linux-kernel@...r.kernel.org, x86@...nel.org
Cc:     tglx@...utronix.de, mingo@...hat.com, bp@...en8.de, hpa@...or.com,
        jon.grimm@....com,
        Sebastian Andrzej Siewior <bigeasy@...utronix.de>,
        Thomas Lendacky <Thomas.Lendacky@....com>
Subject: Re: [PATCH] x86/fpu: Warn only when CPU-provided sizes less than
 struct declaration

On 12/10/19 9:24 PM, Suravee Suthikulpanit wrote:
>>> Yes, the implementation includes the padding size within the size of
>>> the enumerated state. This results in the reported size larger than
>>> the amount needed by the feature.
> 
> Actually, please allow me clarify my understanding for this part.
> 
> When you referred to "the existing architecture for padding", IIUC,
> that's the XSAVE state size, offset, and alignment of each extended
> feature reported by the CPUID Fn 0Dh E[A|B|C]X. By "padding", do you
> mean the additional area included as part of alignment?

I was specifically thinking of this nugget in Intel's SDM, Volume 1, 13.2:

> The value returned by ECX[1] indicates the alignment of state
> component i when the compacted format of the extended region of an
> XSAVE area is used (see Section 13.4.3). If ECX[1] returns 0, state
> component i is located immediately following the preceding state
> component; if ECX[1] returns 1, state component i is located on the
> next 64-byte boundary following the preceding state component.

Essentially, if an implementation needs state alignment or (up to) 64
bytes of padding, it could use this existing architecture for it.

>> I don't think we've ever had XSAVE state that differed in size between
>> implementations.  This kind of thing ensures that we can't have any
>> statically-defined inspection into the XSAVE state.
>>
>> It also increases the amount of blind trust that we have in the CPU
>> implementations.  However, those warnings were specifically added at
>> Ingo's behest (IIRC) to reduce our blind trust in the CPU.
> 
> I am not quite sure what you meant by "statically-defined inspection"

Previously, it was possible to depend on a constant offset for a state
component in an XSAVE buffer.  You could literally say "PKRU is at
offset 0x1234" (or whatever).  All implementations had PKRU in the same
spot (without the compacted format).

BTW, I'm not saying this is a problem.  The documented XSAVE
architecture itself has no provisions for the state being accessed like
this.

> and "blind trust".

I think I actually parroted the term from Ingo:

https://lore.kernel.org/lkml/20150808090615.GA32641@gmail.com/

But the point is that with your patch, the kernel becomes less strict
about what we demand from the CPU.  That might lead to letting CPU bugs
creep in that might cause real problems later.

> Please correct me if I am wrong, but I believe this is similar to the
> case mentioned in the commit ef78f2a4bf84 ('x86/fpu: Check
> CPU-provided sizes against struct declarations'), where it mentions
> inconsistency b/w the MPX 'bndcsr' state and the C structures.

Yep, but I fixed that by padding the C structure, not silencing the
warning.  Also *ALL* MPX implementations have had the same size for that
state.

If we go forward with this patch, we should also removing the
pad_to_64_bytes[] from 'struct mpx_bndcsr_state'.

> What I have been told (by HW folks) is that the hardware reports 32 bytes for PKRU feature
> to account for additional padding (24 bytes) required to maintain offset for the XSAVE data
> in compact form where:
> 
>     offset of the next component = offset of current component +
>                                    size of current component
> 
> In this case, the hardware adds the padding needed before the offset of the subsequent
> feature into the PKRU xsave state size. 

Huh, that's exactly why I thought we added ECX[1]. to the architecture.

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