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Date: Wed, 11 Dec 2019 10:33:39 +0800 From: Yong Wu <yong.wu@...iatek.com> To: Matthias Brugger <matthias.bgg@...il.com> CC: Joerg Roedel <joro@...tes.org>, Robin Murphy <robin.murphy@....com>, Rob Herring <robh+dt@...nel.org>, Evan Green <evgreen@...omium.org>, Tomasz Figa <tfiga@...gle.com>, <linux-mediatek@...ts.infradead.org>, <srv_heupstream@...iatek.com>, <linux-kernel@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>, <iommu@...ts.linux-foundation.org>, <weiyi.lu@...iatek.com>, <yong.wu@...iatek.com>, <youlin.pei@...iatek.com>, Nicolas Boichat <drinkcat@...omium.org>, <anan.sun@...iatek.com>, <ming-fan.chen@...iatek.com>, <cui.zhang@...iatek.com>, <chao.hao@...iatek.com> Subject: [PATCH v2] arm64: dts: Add m4u and smi-larbs nodes for mt8183 Add nodes for M4U, smi-common, and smi-larbs. Signed-off-by: Yong Wu <yong.wu@...iatek.com> --- change notes: v2: Rebase on v5.5-rc1 and power_domain nodes[1]. [1] https://lore.kernel.org/patchwork/patch/1164746/ v1: https://lore.kernel.org/patchwork/patch/1054099/ --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 85 ++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 91217e4f..0f8f78e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/clock/mt8183-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/memory/mt8183-larb-port.h> #include <dt-bindings/power/mt8183-power.h> #include "mt8183-pinfunc.h" @@ -335,6 +336,15 @@ clock-names = "clk13m"; }; + iommu: iommu@...05000 { + compatible = "mediatek,mt8183-m4u"; + reg = <0 0x10205000 0 0x1000>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>; + mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 + &larb4 &larb5 &larb6>; + #iommu-cells = <1>; + }; + auxadc: auxadc@...01000 { compatible = "mediatek,mt8183-auxadc", "mediatek,mt8173-auxadc"; @@ -651,9 +661,25 @@ #clock-cells = <1>; }; + larb0: larb@...17000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x14017000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB0>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clock-names = "apb", "smi"; + }; + smi_common: smi@...19000 { compatible = "mediatek,mt8183-smi-common", "syscon"; reg = <0 0x14019000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_GALS_COMM0>, + <&mmsys CLK_MM_GALS_COMM1>; + clock-names = "apb", "smi", "gals0", "gals1"; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; }; imgsys: syscon@...20000 { @@ -662,18 +688,57 @@ #clock-cells = <1>; }; + larb5: larb@...21000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x15021000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB5>, + <&mmsys CLK_MM_GALS_IMG2MM>; + clock-names = "apb", "smi", "gals"; + power-domains = <&scpsys MT8183_POWER_DOMAIN_ISP>; + }; + + larb2: larb@...2f000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x1502f000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&imgsys CLK_IMG_LARB2>, <&imgsys CLK_IMG_LARB2>, + <&mmsys CLK_MM_GALS_IPU2MM>; + clock-names = "apb", "smi", "gals"; + power-domains = <&scpsys MT8183_POWER_DOMAIN_ISP>; + }; + vdecsys: syscon@...00000 { compatible = "mediatek,mt8183-vdecsys", "syscon"; reg = <0 0x16000000 0 0x1000>; #clock-cells = <1>; }; + larb1: larb@...10000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x16010000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&scpsys MT8183_POWER_DOMAIN_VDEC>; + }; + vencsys: syscon@...00000 { compatible = "mediatek,mt8183-vencsys", "syscon"; reg = <0 0x17000000 0 0x1000>; #clock-cells = <1>; }; + larb4: larb@...10000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x17010000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&vencsys CLK_VENC_LARB>, + <&vencsys CLK_VENC_LARB>; + clock-names = "apb", "smi"; + power-domains = <&scpsys MT8183_POWER_DOMAIN_VENC>; + }; + ipu_conn: syscon@...00000 { compatible = "mediatek,mt8183-ipu_conn", "syscon"; reg = <0 0x19000000 0 0x1000>; @@ -703,5 +768,25 @@ reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; }; + + larb6: larb@...01000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x1a001000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&camsys CLK_CAM_LARB6>, <&camsys CLK_CAM_LARB6>, + <&mmsys CLK_MM_GALS_CAM2MM>; + clock-names = "apb", "smi", "gals"; + power-domains = <&scpsys MT8183_POWER_DOMAIN_CAM>; + }; + + larb3: larb@...02000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x1a002000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&camsys CLK_CAM_LARB3>, <&camsys CLK_CAM_LARB3>, + <&mmsys CLK_MM_GALS_IPU12MM>; + clock-names = "apb", "smi", "gals"; + power-domains = <&scpsys MT8183_POWER_DOMAIN_CAM>; + }; }; }; -- 1.9.1
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