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Date: Thu, 12 Dec 2019 11:55:01 -0800
From: Matthias Kaehlcke <mka@...omium.org>
To: Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>
Cc: devicetree@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-kernel@...r.kernel.org, Rajeshwari <rkambl@...eaurora.org>,
Douglas Anderson <dianders@...omium.org>,
Maulik Shah <mkshah@...eaurora.org>,
Matthias Kaehlcke <mka@...omium.org>
Subject: [PATCH] arm64: dts: qcom: sc7180: Fix order of nodes
The SC7180 device tree nodes should be ordered by address. Re-shuffle
some nodes which currently don't follow this convention.
Signed-off-by: Matthias Kaehlcke <mka@...omium.org>
---
Bjorn/Andy: if this is considered correct could it be landed quickly,
to have a sane baseline for other patches and minimize conflicts?
arch/arm64/boot/dts/qcom/sc7180.dtsi | 74 ++++++++++++++--------------
1 file changed, 37 insertions(+), 37 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 63a7bfb7f5125..286a4b2aeced9 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -619,16 +619,6 @@
};
};
- pdc: interrupt-controller@...0000 {
- compatible = "qcom,sc7180-pdc", "qcom,pdc";
- reg = <0 0xb220000 0 0x30000>;
- qcom,pdc-ranges = <0 480 15>, <17 497 98>,
- <119 634 4>, <124 639 1>;
- #interrupt-cells = <2>;
- interrupt-parent = <&intc>;
- interrupt-controller;
- };
-
tlmm: pinctrl@...0000 {
compatible = "qcom,sc7180-pinctrl";
reg = <0 0x03500000 0 0x300000>,
@@ -932,33 +922,6 @@
status = "disabled";
};
- system-cache-controller@...0000 {
- compatible = "qcom,sc7180-llcc";
- reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
- reg-names = "llcc_base", "llcc_broadcast_base";
- interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- tsens0: thermal-sensor@...3000 {
- compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
- reg = <0 0x0c263000 0 0x1ff>, /* TM */
- <0 0x0c222000 0 0x1ff>; /* SROT */
- #qcom,sensors = <15>;
- interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "uplow";
- #thermal-sensor-cells = <1>;
- };
-
- tsens1: thermal-sensor@...5000 {
- compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
- reg = <0 0x0c265000 0 0x1ff>, /* TM */
- <0 0x0c223000 0 0x1ff>; /* SROT */
- #qcom,sensors = <10>;
- interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "uplow";
- #thermal-sensor-cells = <1>;
- };
-
usb_1_hsphy: phy@...3000 {
compatible = "qcom,sc7180-qusb2-phy";
reg = <0 0x088e3000 0 0x400>;
@@ -1007,6 +970,13 @@
};
};
+ system-cache-controller@...0000 {
+ compatible = "qcom,sc7180-llcc";
+ reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
+ reg-names = "llcc_base", "llcc_broadcast_base";
+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
usb_1: usb@...8800 {
compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
@@ -1051,6 +1021,36 @@
};
};
+ pdc: interrupt-controller@...0000 {
+ compatible = "qcom,sc7180-pdc", "qcom,pdc";
+ reg = <0 0xb220000 0 0x30000>;
+ qcom,pdc-ranges = <0 480 15>, <17 497 98>,
+ <119 634 4>, <124 639 1>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
+ tsens0: thermal-sensor@...3000 {
+ compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
+ reg = <0 0x0c263000 0 0x1ff>, /* TM */
+ <0 0x0c222000 0 0x1ff>; /* SROT */
+ #qcom,sensors = <15>;
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow";
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens1: thermal-sensor@...5000 {
+ compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
+ reg = <0 0x0c265000 0 0x1ff>, /* TM */
+ <0 0x0c223000 0 0x1ff>; /* SROT */
+ #qcom,sensors = <10>;
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow";
+ #thermal-sensor-cells = <1>;
+ };
+
spmi_bus: spmi@...0000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0 0x0c440000 0 0x1100>,
--
2.24.1.735.g03f4e72817-goog
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