lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Thu, 12 Dec 2019 16:20:16 +0100
From:   Michal Simek <michal.simek@...inx.com>
To:     Rajan Vaja <rajan.vaja@...inx.com>, mturquette@...libre.com,
        sboyd@...nel.org, robh+dt@...nel.org, mark.rutland@....com,
        michal.simek@...inx.com, jolly.shah@...inx.com,
        m.tretter@...gutronix.de, gustavo@...eddedor.com,
        tejas.patel@...inx.com, nava.manne@...inx.com, mdf@...nel.org
Cc:     linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v3 0/6] clk: zynqmp: Extend and fix zynqmp clock driver

On 05. 12. 19 7:35, Rajan Vaja wrote:
> ZynqMP clock driver can be used for Versal platform also. Add support
> for Versal platform in ZynqMP clock driver.
> 
> Also this patch series fixes divider calculation and adds support for get
> maximum divider, clock with CLK_DIVIDER_POWER_OF_TWO flag and warn user if
> clock users are more than allowed.
> 
> Rajan Vaja (5):
>   dt-bindings: clock: Add bindings for versal clock driver
>   clk: zynqmp: Extend driver for versal
>   clk: zynqmp: Warn user if clock user are more than allowed
>   clk: zynqmp: Add support for get max divider
>   clk: zynqmp: Fix divider calculation
> 
> Tejas Patel (1):
>   clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag
> 
>  .../devicetree/bindings/clock/xlnx,versal-clk.yaml |  64 +++++++++++
>  drivers/clk/zynqmp/clkc.c                          |   3 +-
>  drivers/clk/zynqmp/divider.c                       | 118 +++++++++++++++++++-
>  drivers/clk/zynqmp/pll.c                           |   6 +-
>  drivers/firmware/xilinx/zynqmp.c                   |   2 +
>  include/dt-bindings/clock/xlnx-versal-clk.h        | 123 +++++++++++++++++++++
>  include/linux/firmware/xlnx-zynqmp.h               |   2 +
>  7 files changed, 310 insertions(+), 8 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
>  create mode 100644 include/dt-bindings/clock/xlnx-versal-clk.h
> 

That firmware changes looks good. That's why feel free to add my
Acked-by: Michal Simek <michal.simek@...inx.com>
to that patches.
If you want me to take it via my tree please let me know.

Thanks,
Michal

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ