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Message-ID: <CAGb2v65EBb-qvb6XVzvZgqKUbzJJgkXgB5y2uA8Aa1__n9v+qw@mail.gmail.com>
Date: Fri, 13 Dec 2019 16:08:12 +0800
From: Chen-Yu Tsai <wens@...e.org>
To: Marek Szyprowski <m.szyprowski@...sung.com>,
Maxime Ripard <mripard@...nel.org>
Cc: linux-usb <linux-usb@...r.kernel.org>,
"moderated list:ARM/SAMSUNG EXYNO..."
<linux-samsung-soc@...r.kernel.org>,
"moderated list:ARM/Mediatek SoC..."
<linux-mediatek@...ts.infradead.org>,
linux-kernel <linux-kernel@...r.kernel.org>,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Krzysztof Kozlowski <krzk@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Stefan Agner <stefan@...er.ch>,
Chunfeng Yun <chunfeng.yun@...iatek.com>,
Linus Walleij <linus.walleij@...aro.org>,
Bartlomiej Zolnierkiewicz <b.zolnierkie@...sung.com>
Subject: Re: [PATCH v2 3/4] ARM: dts: sun8i: a83t: Correct USB3503 GPIOs polarity
On Wed, Dec 11, 2019 at 10:52 PM Marek Szyprowski
<m.szyprowski@...sung.com> wrote:
>
> Current USB3503 driver ignores GPIO polarity and always operates as if the
> GPIO lines were flagged as ACTIVE_HIGH. Fix the polarity for the existing
> USB3503 chip applications to match the chip specification and common
> convention for naming the pins. The only pin, which has to be ACTIVE_LOW
> is the reset pin. The remaining are ACTIVE_HIGH. This change allows later
> to fix the USB3503 driver to properly use generic GPIO bindings and read
> polarity from DT.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@...sung.com>
Acked-by: Chen-Yu Tsai <wens@...e.org>
I assume the dts patch has to go in before or at the same time as the driver
patch?
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