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Message-ID: <20191213195208.GB13693@bogus>
Date: Fri, 13 Dec 2019 13:52:08 -0600
From: Rob Herring <robh@...nel.org>
To: shubhrajyoti.datta@...il.com
Cc: linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
devel@...verdev.osuosl.org, gregkh@...uxfoundation.org,
mturquette@...libre.com, sboyd@...nel.org, mark.rutland@....com,
devicetree@...r.kernel.org, soren.brinkmann@...inx.com,
Shubhrajyoti Datta <shubhrajyoti.datta@...inx.com>
Subject: Re: [PATCH v3 01/10] dt-bindings: add documentation of xilinx
clocking wizard
On Thu, Nov 28, 2019 at 12:06:08PM +0530, shubhrajyoti.datta@...il.com wrote:
> From: Shubhrajyoti Datta <shubhrajyoti.datta@...inx.com>
>
> Add the devicetree binding for the xilinx clocking wizard.
>
> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@...inx.com>
> ---
> .../bindings/clock/xlnx,clocking-wizard.txt | 32 ++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.txt
New bindings should be in DT schema format.
>
> diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.txt b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.txt
> new file mode 100644
> index 0000000..aedac84
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.txt
> @@ -0,0 +1,32 @@
> +Binding for Xilinx Clocking Wizard IP Core
> +
> +This binding uses the common clock binding[1]. Details about the devices can be
> +found in the product guide[2].
> +
> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +[2] Clocking Wizard Product Guide
> +http://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v5_1/pg065-clk-wiz.pdf
> +
> +Required properties:
> + - compatible: Must be 'xlnx,clocking-wizard'
That's not very specific. Is there only 1 version of this h/w?
> + - #clock-cells: Number of cells in a clock specifier. Should be 1
> + - reg: Base and size of the cores register space
> + - clocks: Handle to input clock
> + - clock-names: Tuple containing 'clk_in1' and 's_axi_aclk'
> + - clock-output-names: Names for the output clocks
You have to define the values.
> +
> +Optional properties:
> + - speed-grade: Speed grade of the device (valid values are 1..3)
> +
> +Example:
> + clock-generator@...40000 {
> + #clock-cells = <1>;
> + reg = <0x40040000 0x1000>;
> + compatible = "xlnx,clocking-wizard";
> + speed-grade = <1>;
> + clock-names = "clk_in1", "s_axi_aclk";
> + clocks = <&clkc 15>, <&clkc 15>;
> + clock-output-names = "clk_out0", "clk_out1", "clk_out2",
> + "clk_out3", "clk_out4", "clk_out5",
> + "clk_out6", "clk_out7";
Don't really need this to be in DT given all the names are the same
except for the index.
Rob
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