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Message-Id: <20191215165924.28314-2-wens@kernel.org>
Date: Mon, 16 Dec 2019 00:59:11 +0800
From: Chen-Yu Tsai <wens@...nel.org>
To: Maxime Ripard <mripard@...nel.org>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Sakari Ailus <sakari.ailus@...ux.intel.com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>
Cc: Chen-Yu Tsai <wens@...nel.org>, linux-media@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Chen-Yu Tsai <wens@...e.org>
Subject: [PATCH 01/14] dt-bindings: media: sun4i-csi: Add compatible for CSI1 on A10/A20
From: Chen-Yu Tsai <wens@...e.org>
The CSI1 block has the same structure and layout as the CSI0 block.
Differences include:
- Only one channel in BT.656 instead of four in CSI0
- 10-bit raw data input vs 8-bit in CSI0
- 24-bit RGB888/YUV444 input vs 16-bit RGB565/YUV422 in CSI0
- No ISP hardware
The hardware found in the A20 is the same as in the A10.
Signed-off-by: Chen-Yu Tsai <wens@...e.org>
---
.../bindings/media/allwinner,sun4i-a10-csi.yaml | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml
index d3e423fcb6c2..221fe630c7d5 100644
--- a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml
+++ b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml
@@ -16,7 +16,12 @@ description: |-
properties:
compatible:
- const: allwinner,sun7i-a20-csi0
+ oneOf:
+ - const: allwinner,sun4i-a10-csi1
+ - const: allwinner,sun7i-a20-csi0
+ - items:
+ - const: allwinner,sun7i-a20-csi1
+ - const: allwinner,sun4i-a10-csi1
reg:
maxItems: 1
@@ -25,12 +30,16 @@ properties:
maxItems: 1
clocks:
+ minItems: 2
+ maxItems: 3
items:
- description: The CSI interface clock
- description: The CSI ISP clock
- description: The CSI DRAM clock
clock-names:
+ minItems: 2
+ maxItems: 3
items:
- const: bus
- const: isp
--
2.24.0
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