linux-kernel - Re: [PATCH 03/14] media: sun4i-csi: Fix data sampling polarity handling

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Message-ID: <20191216133603.gbr2iaikch5lfv6v@gilmour.lan>
Date:   Mon, 16 Dec 2019 14:36:03 +0100
From:   Maxime Ripard <mripard@...nel.org>
To:     Chen-Yu Tsai <wens@...nel.org>
Cc:     Mauro Carvalho Chehab <mchehab@...nel.org>,
        Sakari Ailus <sakari.ailus@...ux.intel.com>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        linux-media@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        Chen-Yu Tsai <wens@...e.org>
Subject: Re: [PATCH 03/14] media: sun4i-csi: Fix data sampling polarity
 handling

On Mon, Dec 16, 2019 at 12:59:13AM +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai <wens@...e.org>
>
> The CLK_POL field specifies whether data is sampled on the falling or
> rising edge of PCLK, not whether the data lines are active high or low.
> Evidence of this can be found in the timing diagram labeled "horizontal
> size setting and pixel clock timing".
>
> Fix the setting by checking the correct flag, V4L2_MBUS_PCLK_SAMPLE_RISING.
> While at it, reorder the three polarity flag checks so HSYNC and VSYNC
> are grouped together.
>
> Fixes: 577bbf23b758 ("media: sunxi: Add A10 CSI driver")
> Signed-off-by: Chen-Yu Tsai <wens@...e.org>

Acked-by: Maxime Ripard <mripard@...nel.org>

Thanks!
Maxime

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