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Date:   Mon, 16 Dec 2019 14:38:14 +0100
From:   Maxime Ripard <mripard@...nel.org>
To:     Chen-Yu Tsai <wens@...nel.org>
Cc:     Mauro Carvalho Chehab <mchehab@...nel.org>,
        Sakari Ailus <sakari.ailus@...ux.intel.com>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        linux-media@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        Chen-Yu Tsai <wens@...e.org>
Subject: Re: [PATCH 05/14] media: sun4i-csi: Deal with DRAM offset

On Mon, Dec 16, 2019 at 12:59:15AM +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai <wens@...e.org>
>
> On Allwinner SoCs, some high memory bandwidth devices do DMA directly
> over the memory bus (called MBUS), instead of the system bus. These
> devices include the CSI camera sensor interface, video (codec) engine,
> display subsystem, etc.. The memory bus has a different addressing
> scheme without the DRAM starting offset.
>
> Deal with this using the "interconnects" property from the device tree,
> or if that is not available, set dev->dma_pfn_offset to PHYS_PFN_OFFSET.
>
> Fixes: 577bbf23b758 ("media: sunxi: Add A10 CSI driver")
> Signed-off-by: Chen-Yu Tsai <wens@...e.org>

Acked-by: Maxime Ripard <mripard@...nel.org>

> ---
>  .../platform/sunxi/sun4i-csi/sun4i_csi.c      | 22 +++++++++++++++++++
>  1 file changed, 22 insertions(+)
>
> diff --git a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c
> index f36dc6258900..b8b07c1de2a8 100644
> --- a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c
> +++ b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c
> @@ -11,6 +11,7 @@
>  #include <linux/module.h>
>  #include <linux/mutex.h>
>  #include <linux/of.h>
> +#include <linux/of_device.h>
>  #include <linux/of_graph.h>
>  #include <linux/platform_device.h>
>  #include <linux/pm_runtime.h>
> @@ -155,6 +156,27 @@ static int sun4i_csi_probe(struct platform_device *pdev)
>  	subdev = &csi->subdev;
>  	vdev = &csi->vdev;
>
> +	/*
> +	 * On Allwinner SoCs, some high memory bandwidth devices do DMA
> +	 * directly over the memory bus (called MBUS), instead of the
> +	 * system bus. The memory bus has a different addressing scheme
> +	 * without the DRAM starting offset.
> +	 *
> +	 * In some cases this can be described by an interconnect in
> +	 * the device tree. In other cases where the hardware is not
> +	 * fully understood and the interconnect is left out of the
> +	 * device tree, fall back to a default offset.
> +	 */

Though we should probably mention the DT-backward-compatibility case
here too.

Maxime

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