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Message-ID: <fe28c214-f86b-b849-78e8-f879185269f7@codeaurora.org>
Date: Tue, 17 Dec 2019 16:01:53 +0530
From: Rajendra Nayak <rnayak@...eaurora.org>
To: Sibi Sankar <sibis@...eaurora.org>, bjorn.andersson@...aro.org,
robh+dt@...nel.org
Cc: agross@...nel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-msm@...r.kernel.org,
mark.rutland@....com, swboyd@...omium.org, dianders@...omium.org
Subject: Re: [PATCH 2/2] arm64: dts: qcom: sc7180: Add rpmh power-domain node
On 12/16/2019 5:25 PM, Sibi Sankar wrote:
> Add the DT node for the rpmhpd power controller on SC7180 SoCs.
>
> Signed-off-by: Sibi Sankar <sibis@...eaurora.org>
> ---
Reviewed-by: Rajendra Nayak <rnayak@...eaurora.org>
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 55 ++++++++++++++++++++++++++++
> 1 file changed, 55 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 01bbb58ae5160..fb17dc62d7ab1 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -9,6 +9,7 @@
> #include <dt-bindings/clock/qcom,rpmh.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/phy/phy-qcom-qusb2.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>
> / {
> @@ -1284,6 +1285,60 @@
> clock-names = "xo";
> #clock-cells = <1>;
> };
> +
> + rpmhpd: power-controller {
> + compatible = "qcom,sc7180-rpmhpd";
> + #power-domain-cells = <1>;
> + operating-points-v2 = <&rpmhpd_opp_table>;
> +
> + rpmhpd_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + rpmhpd_opp_ret: opp1 {
> + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
> + };
> +
> + rpmhpd_opp_min_svs: opp2 {
> + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> + };
> +
> + rpmhpd_opp_low_svs: opp3 {
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> + };
> +
> + rpmhpd_opp_svs: opp4 {
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> + };
> +
> + rpmhpd_opp_svs_l1: opp5 {
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> + };
> +
> + rpmhpd_opp_svs_l2: opp6 {
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
> + };
> +
> + rpmhpd_opp_nom: opp7 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> + };
> +
> + rpmhpd_opp_nom_l1: opp8 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> + };
> +
> + rpmhpd_opp_nom_l2: opp9 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
> + };
> +
> + rpmhpd_opp_turbo: opp10 {
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> + };
> +
> + rpmhpd_opp_turbo_l1: opp11 {
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> + };
> + };
> + };
> };
>
> cpufreq_hw: cpufreq@...23000 {
>
--
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