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Message-Id: <20191218143332.29107-1-sibis@codeaurora.org>
Date: Wed, 18 Dec 2019 20:03:32 +0530
From: Sibi Sankar <sibis@...eaurora.org>
To: agross@...nel.org, bjorn.andersson@...aro.org, robh+dt@...nel.org
Cc: mark.rutland@....com, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
mka@...omium.org, swboyd@...omium.org, dianders@...omium.org,
Sibi Sankar <sibis@...eaurora.org>
Subject: [PATCH] arm64: dts: qcom: sc7180: Enable multiple nodes
Add scm, smem, smp2p, aoss-qmp, aoss-cc and pdc-global device nodes
to SC7180 SoCs.
Signed-off-by: Sibi Sankar <sibis@...eaurora.org>
---
Depends on https://patchwork.kernel.org/patch/11289689/
I'll probably need to re-spin the patch once Rob decides on how to name
the reserved-memory nodes.
arch/arm64/boot/dts/qcom/sc7180.dtsi | 126 +++++++++++++++++++++++++++
1 file changed, 126 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 8903f9afe62f6..4e3f092093925 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -9,7 +9,10 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
+#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/reset/qcom,sdm845-aoss.h>
+#include <dt-bindings/reset/qcom,sdm845-pdc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
@@ -65,6 +68,10 @@
aop_cmd_db_mem: memory@...20000 {
reg = <0x0 0x80820000 0x0 0x20000>;
compatible = "qcom,cmd-db";
+ };
+
+ smem_mem: memory@...00000 {
+ reg = <0x0 0x80900000 0x0 0x200000>;
no-map;
};
};
@@ -192,6 +199,92 @@
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
};
+ firmware {
+ scm {
+ compatible = "qcom,scm-sc7180", "qcom,scm";
+ };
+ };
+
+ tcsr_mutex: hwlock {
+ compatible = "qcom,tcsr-mutex";
+ syscon = <&tcsr_mutex_regs 0 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_mem>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ smp2p-cdsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <94>, <432>;
+
+ interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&apss_shared 6>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ cdsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ cdsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-lpass {
+ compatible = "qcom,smp2p";
+ qcom,smem = <443>, <429>;
+
+ interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&apss_shared 10>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+
+ adsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ adsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-mpss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+ interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&apss_shared 14>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ modem_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ modem_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -643,6 +736,11 @@
};
};
+ tcsr_mutex_regs: syscon@...0000 {
+ compatible = "syscon";
+ reg = <0 0x01f40000 0 0x40000>;
+ };
+
tlmm: pinctrl@...0000 {
compatible = "qcom,sc7180-pinctrl";
reg = <0 0x03500000 0 0x300000>,
@@ -1052,6 +1150,12 @@
interrupt-controller;
};
+ pdc_reset: reset-controller@...0000 {
+ compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
+ reg = <0 0x0b2e0000 0 0x20000>;
+ #reset-cells = <1>;
+ };
+
tsens0: thermal-sensor@...3000 {
compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
reg = <0 0x0c263000 0 0x1ff>, /* TM */
@@ -1072,6 +1176,22 @@
#thermal-sensor-cells = <1>;
};
+ aoss_reset: reset-controller@...0000 {
+ compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
+ reg = <0 0x0c2a0000 0 0x31000>;
+ #reset-cells = <1>;
+ };
+
+ aoss_qmp: qmp@...0000 {
+ compatible = "qcom,sc7180-aoss-qmp";
+ reg = <0 0x0c300000 0 0x100000>;
+ interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&apss_shared 0>;
+
+ #clock-cells = <0>;
+ #power-domain-cells = <1>;
+ };
+
spmi_bus: spmi@...0000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0 0x0c440000 0 0x1100>,
@@ -1199,6 +1319,12 @@
};
};
+ apss_shared: mailbox@...00000 {
+ compatible = "qcom,sc7180-apss-shared";
+ reg = <0 0x17c00000 0 0x10000>;
+ #mbox-cells = <1>;
+ };
+
watchdog@...10000 {
compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
--
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