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Message-ID: <437f2bff-13ba-0ae9-2f3c-bc8eb82d20f0@nvidia.com>
Date: Fri, 20 Dec 2019 16:41:35 -0800
From: John Hubbard <jhubbard@...dia.com>
To: Dan Williams <dan.j.williams@...el.com>, Jan Kara <jack@...e.cz>
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Subject: Re: [PATCH v11 00/25] mm/gup: track dma-pinned pages: FOLL_PIN
On 12/20/19 4:33 PM, Dan Williams wrote:
...
>> I believe there might be also a different solution for this: For
>> transparent huge pages, we could find a space in 'struct page' of the
>> second page in the huge page for proper pin counter and just account pins
>> there so we'd have full width of 32-bits for it.
>
> That would require THP accounting for dax pages. It is something that
> was probably going to be needed, but this would seem to force the
> issue.
>
Thanks for mentioning that, it wasn't obvious to me yet.
How easy is it for mere mortals outside of Intel, to set up a DAX (nvdimm?)
test setup? I'd hate to go into this without having that coverage up
and running. It's been sketchy enough as it is. :)
thanks,
--
John Hubbard
NVIDIA
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