linux-kernel - [PATCH v2 07/14] dt-bindings: phy: phy-cadence-torrent: Add clock bindings

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <1577114139-14984-8-git-send-email-yamonkar@cadence.com>
Date:   Mon, 23 Dec 2019 16:15:32 +0100
From:   Yuti Amonkar <yamonkar@...ence.com>
To:     <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <kishon@...com>, <robh+dt@...nel.org>, <mark.rutland@....com>,
        <maxime@...no.tech>
CC:     <jsarha@...com>, <tomi.valkeinen@...com>, <praneeth@...com>,
        <mparab@...ence.com>, <sjakhade@...ence.com>,
        <yamonkar@...ence.com>
Subject: [PATCH v2 07/14] dt-bindings: phy: phy-cadence-torrent: Add clock bindings

Add Torrent PHY reference clock bindings.This will not affect ABI as
the driver has never been functional, and therefore do not exist in
any active use case

Signed-off-by: Yuti Amonkar <yamonkar@...ence.com>
---
 .../devicetree/bindings/phy/phy-cadence-torrent.yaml         | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
index 3587312..907b627 100644
--- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
@@ -17,6 +17,14 @@ properties:
   compatible:
     const: cdns,torrent-phy
 
+  clocks:
+    maxItems: 1
+    description:
+      PHY reference clock. Must contain an entry in clock-names.
+
+  clock-names:
+    const: refclk
+
   reg:
     items:
       - description: Offset of the DPTX PHY configuration registers.
@@ -46,6 +54,8 @@ properties:
 
 required:
   - compatible
+  - clocks
+  - clock-names
   - reg
   - "#phy-cells"
 
@@ -60,5 +70,7 @@ examples:
           num_lanes = <4>;
           max_bit_rate = <8100>;
           #phy-cells = <0>;
+          clocks = <&ref_clk>;
+          clock-names = "refclk";
     };
 ...
-- 
2.7.4