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Message-ID: <ac2f6bf823e27fe51780be7a82541991@codeaurora.org>
Date: Tue, 24 Dec 2019 13:55:57 +0800
From: Can Guo <cang@...eaurora.org>
To: Vinod Koul <vkoul@...nel.org>
Cc: Kishon Vijay Abraham I <kishon@...com>,
linux-arm-msm@...r.kernel.org,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Andy Gross <agross@...nel.org>,
Jeffrey Hugo <jeffrey.l.hugo@...il.com>,
Manu Gautam <mgautam@...eaurora.org>,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 4/4] phy: qcom-qmp: Add SW reset register
On 2019-12-23 22:30, Vinod Koul wrote:
> For V4 QMP UFS Phy, we need to assert reset bits, configure the phy and
> then deassert it, so add the QPHY_SW_RESET register which does this.
>
> Signed-off-by: Vinod Koul <vkoul@...nel.org>
Reviewed-by: Can Guo <cang@...eaurora.org>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
> b/drivers/phy/qualcomm/phy-qcom-qmp.c
> index ce5e18f188c3..7db2a94f7a99 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> @@ -168,6 +168,7 @@ static const unsigned int
> sdm845_ufsphy_regs_layout[] = {
> static const unsigned int sm8150_ufsphy_regs_layout[] = {
> [QPHY_START_CTRL] = QPHY_V4_PHY_START,
> [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_READY_STATUS,
> + [QPHY_SW_RESET] = QPHY_V4_SW_RESET,
> };
>
> static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
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