linux-kernel - Re: [PATCH v24 07/24] x86/cpu/intel: Detect SGX supprt

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Message-ID: <05875955d6a4de39a2686ac62e7b2b8583450b49.camel@linux.intel.com>
Date:   Fri, 27 Dec 2019 08:00:50 +0200
From:   Jarkko Sakkinen <jarkko.sakkinen@...ux.intel.com>
To:     Borislav Petkov <bp@...en8.de>
Cc:     linux-kernel@...r.kernel.org, x86@...nel.org,
        linux-sgx@...r.kernel.org, akpm@...ux-foundation.org,
        dave.hansen@...el.com, sean.j.christopherson@...el.com,
        nhorman@...hat.com, npmccallum@...hat.com, serge.ayoun@...el.com,
        shay.katz-zamir@...el.com, haitao.huang@...el.com,
        andriy.shevchenko@...ux.intel.com, tglx@...utronix.de,
        kai.svahn@...el.com, josh@...htriplett.org, luto@...nel.org,
        kai.huang@...el.com, rientjes@...gle.com, cedric.xing@...el.com,
        puiterwijk@...hat.com
Subject: Re: [PATCH v24 07/24] x86/cpu/intel: Detect SGX supprt

On Mon, 2019-12-23 at 10:46 +0100, Borislav Petkov wrote:
> On Sat, Nov 30, 2019 at 01:13:09AM +0200, Jarkko Sakkinen wrote:
> > From: Sean Christopherson <sean.j.christopherson@...el.com>
> > 
> > When the CPU supports SGX, check that the BIOS has enabled SGX and SGX1
> > opcodes are available. Otherwise, all the SGX related capabilities.
> > 
> > In addition, clear X86_FEATURE_SGX_LC also in the case when the launch
> > enclave are read-only. This way the feature bit reflects the level that
> > Linux supports the launch control.
> > 
> > The check is done for every CPU, not just BSP, in order to verify that
> > MSR_IA32_FEATURE_CONTROL is correctly configured on all CPUs. The other
> > parts of the kernel, like the enclave driver, expect the same
> > configuration from all CPUs.
> > 
> > Signed-off-by: Sean Christopherson <sean.j.christopherson@...el.com>
> > Co-developed-by: Jarkko Sakkinen <jarkko.sakkinen@...ux.intel.com>
> > Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@...ux.intel.com>
> > ---
> >  arch/x86/kernel/cpu/intel.c | 41 +++++++++++++++++++++++++++++++++++++
> >  1 file changed, 41 insertions(+)
> > 
> > diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
> > index c2fdc00df163..89a71367716c 100644
> > --- a/arch/x86/kernel/cpu/intel.c
> > +++ b/arch/x86/kernel/cpu/intel.c
> > @@ -624,6 +624,42 @@ static void detect_tme(struct cpuinfo_x86 *c)
> >  	c->x86_phys_bits -= keyid_bits;
> >  }
> >  
> > +static void __maybe_unused detect_sgx(struct cpuinfo_x86 *c)
> > +{
> > +	unsigned long long fc;
> > +
> > +	rdmsrl(MSR_IA32_FEATURE_CONTROL, fc);
> > +	if (!(fc & FEATURE_CONTROL_LOCKED)) {
> > +		pr_err_once("sgx: The feature control MSR is not locked\n");
> > +		goto err_unsupported;
> > +	}
> > +
> > +	if (!(fc & FEATURE_CONTROL_SGX_ENABLE)) {
> > +		pr_err_once("sgx: SGX is not enabled in IA32_FEATURE_CONTROL MSR\n");
> > +		goto err_unsupported;
> > +	}
> > +
> > +	if (!cpu_has(c, X86_FEATURE_SGX1)) {
> > +		pr_err_once("sgx: SGX1 instruction set is not supported\n");
> > +		goto err_unsupported;
> > +	}
> > +
> > +	if (!(fc & FEATURE_CONTROL_SGX_LE_WR)) {
> > +		pr_info_once("sgx: The launch control MSRs are not writable\n");
> > +		goto err_msrs_rdonly;
> > +	}
> 
> One more thing - and we talked about this already - when the hash
> MSRs are not writable, the kernel needs to disable all SGX support by
> default. Basically, no SGX support is present.
> 
> If the user wants to run KVM guests with SGX enclaves, then she should
> probably boot with a special kvm param or so. Details on how can exactly
> control that can be discussed later - just making sure you guys are not
> forgetting this use angle.
> 
> Thx.

Sure.

Overally, I guess the right marching order is to hold on with the 
next version of SGX patch set up until Sean's other patch set is
ready to be merged.

/Jarkko