linux-kernel - [PATCH] arm64: dts: sc7180: Add clock controller nodes

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Message-Id: <1577435867-32254-1-git-send-email-tdas@codeaurora.org>
Date:   Fri, 27 Dec 2019 14:07:47 +0530
From:   Taniya Das <tdas@...eaurora.org>
To:     agross@...nel.org, robh+dt@...nel.org, bjorn.andersson@...aro.org
Cc:     inux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, mka@...omium.org,
        swboyd@...omium.org, Rajendra Nayak <rnayak@...eaurora.org>,
        Taniya Das <tdas@...eaurora.org>
Subject: [PATCH] arm64: dts: sc7180: Add clock controller nodes

Add the display, video & graphics clock controller nodes supported on
SC7180.

Signed-off-by: Taniya Das <tdas@...eaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 3676bfd..3bb7b65 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -931,6 +931,18 @@
 			};
 		};

+		gpucc: clock-controller@...0000 {
+			compatible = "qcom,sc7180-gpucc";
+			reg = <0 0x05090000 0 0x9000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+			clock-names = "bi_tcxo", "gpll0_main", "gpll0_div";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
 		qspi: spi@...c000 {
 			compatible = "qcom,qspi-v1";
 			reg = <0 0x088dc000 0 0x600>;
@@ -1043,6 +1055,27 @@
 			};
 		};

+		videocc: clock-controller@...0000 {
+			compatible = "qcom,sc7180-videocc";
+			reg = <0 0x0ab00000 0 0x10000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "bi_tcxo";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		dispcc: clock-controller@...0000 {
+			compatible = "qcom,sc7180-dispcc";
+			reg = <0 0x0af00000 0 0x200000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_DISP_GPLL0_CLK_SRC>;
+			clock-names = "bi_tcxo", "gpll0";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
 		pdc: interrupt-controller@...0000 {
 			compatible = "qcom,sc7180-pdc", "qcom,pdc";
 			reg = <0 0x0b220000 0 0x30000>;
--
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